Design And Implementation Of Low-leakage SRAM On 130nm Technology

The proportion of area occupied by SRAM in SoC chips is increasing day by day.Low-power SoCs require the SRAM to retain data in sleep mode.The leakage power of SRAM becomes the main part of SoC power consumption in sleep mode.With the progress of the process,the transistor threshold voltage is getting lower and lower,and the SRAM leakage influences the power consumption of the chip more seriously.Reducing the data retention voltage(DRV)of the bitcell can reduce its leakage,but the reduction of the DRV will weaken the data retention capacity of the bitcell.In the thesis,the DRV distribution of SRAM cell under different process corners is obtained through Monte Carlo analysis.According to the distribution of DRV,the minimum DRV that SRAM can work on the premise of holding data can be determined.When the data is retentive under the minimum DRV,the leakage of thee SRAM is minimum.Reverse biasing of the transistor substrate can increase the threshold voltage and thus reduce the leakage current.In the thesis,the leakage of bitcell under different bias situations is analyzed.Based on the analysis results,a reasonable circuit design scheme is determined.This low-leakage design scheme first divides the SRAM into two voltage domains,VDD and VDDP,to reduce the leakage of the sleep mode.Two internal power supplies,VDDC and VSSC,are used in the voltage domain VDD to power the memory array under the sleep mode.The voltage difference between VDDC and VSSC is the value of DRV.The substrate of the memory array is connected to the top-level power supplies,VDD and VSS,to reverse bias the transistor substrate in the bitcell and reduce the leakage of the memory array.The voltages of VDDC and VSSC are controlled by the DRV control circuit.The feedback regulation of the circuit ensures that the DRV is stable at different process corners.The value of DRV is determined by the reference voltage of the control circuit.In a word,the reference voltage of the DRV control circuit determines the voltages of VDDC and VSSC,and the voltages of VDDC and VSSC determine the DRV.By controlling the reference voltage,the circuit can make the DRV take different values,and the circuit has different low leakage yields under different DRVs.Based on GF 130nm,it is designed a low-leakage SRAM with a capacity of 8KB.The working voltage is 1.2V and the overall circuit area is 0.259mm~2.Compared with the SRAM generated by Memory Compiler,the circuit area increased by 7.9%.The worst-case SRAM read/write delay does not exceed 8 ns,and the test current of data retention state is 47.2nA.Compared with the Memory Compiler,the leakage current is reduced by 78.8%.