Research And Implementation Of PLL Based On Sampling Phase Locking And Digital Phase Locking

China’s national defense is growing rapidly,In radar,communication,figure and so on the many kinds of microwave frequency source in the system transfer part put forward the demands,,Request is also more and more high,Low phase noise of demands,high integration,low voltage and low power consumption,high reliability and so on are evident。In order to be able to meet the requirements for phase noise performance requirements required by the system,PDRO-sampling phase-locked oscillator became often choose.In china,for the high requirement of reliability of military products,can meet the requirements of domestic manufacturers is less,many PDRO products will have to rely on imports,in order to meet the market demand,this thesis designed a sampling phase-locked oscillator and a digital phase-locked LC oscillator phase-locked source,and compared.In this thesis,the following aspects of research and design work.Further study of oscillator related theory,mainly including microwave oscillator circuit structure part,the methods for judging method,determination methods including the rule of Nyquist criterion and negative resistance criterion,the theory of dielectric resonator,oscillator circuit theory analysis of the common medium.Further study of sampling phase-locked technology and relevant theories of digital phase locking technique and the related circuit composition,working principle of sampling phase discriminator,relevant sampling phase-locked circuit composition,phase discriminator circuit including power supply circuit,sampling circuit,loop filter,enlarge circuit,composed of digital phase-locked loop,for digital phase-locked principle analysis,including target analysis,failure analysis,the transfer function of digital phase locking,and the phase noise in oscillators and concrete analysis of phase-locked loop,through these studies,in order to carry out the design of the follow-up work.The design includes two PLL,one for the 10 GHz sample lock and one for the 10 GHz digital locked LC oscillator.The circuit designed in sampling phase-locked DRO,filter,coupler,sampling and phaselocked circuit.The DRO design using PCB technology and MMIC combination of resonator circuit simulation software,and the negative resistance circuit chip according to the design form after the joint simulation,design the DRO circuit design;sampling PLL part and a power supply circuit,sampling circuit,phase detection circuit,signal acquisition circuit,reference method loop filter circuit,the circuit is integrated in a PCB,the circuit by using PCB technology,the use of the device and package patch resistor,capacitor,inductor circuit.Combination of two circuits,the circuit debugging and testing,completed a PDRO product.The hardware circuit design of digital PLL in LC oscillator circuit,including HMC704 digital phase-locked loop filter,digital control circuit,voltage regulator circuit,output amplifier circuit based on the simulation of loop filter and microstrip line,and complete the hardware circuit design of digital PLL using multilayer PCB technology,and through the C language code,configuration of digital PLL ring,complete PLL digital phase-locked LC oscillator.The two phase-locked source is tested and debugged in detail.The recorded data are analyzed,and the final test results are presented.The two PLL sources designed in this thesis meet the requirements.