The FPGA Implementation Of Gzip Lossless Compression Based On HLS

With the period of big data coming,a lot of information needs to be transmitted over the Internet.Network resources increasing bring great pressure on the network transmission.Data compression technology can save data storage space,transmission time and bandwidth,thus it could alleviate the transmission pressure.Gzip lossless compression is the most commonly compression tool,widely used in network data download,data backup and other fields.The open source zlib is the most famous implementation of the Gzip algorithm.However,its large computational complexity result in lower data throughput.FPGA in the data processing speed has the huge advantage which the common processor can not match,but the hardware development usually need to consume a long period.In order to shorten the development cycle,Xilinx company introduced advanced synthesis tools Vivado-HLS,which can directly translate C/C + +,System C and other high-level programming language description of the algorithm or behavior level into the hardware circuits and do RTL-level simulation.Compared to traditional hardware development process,using advanced synthesis tools easier achieve the design module simulation verification and iterative optimization,which greatly shorten the hardware development cycle.In order to solve the problem of Gzip compression throughput would being low,this paper based on the characteristics of the algorithm,designs the pipeline and parallel structure suitable for hardware implementation.On this basis,achieve this structure based on VivadoHLS tool.The main work of this paper is:1.A multi-level pipeline structure of Gzip compression design architecture is proposed.The compression process is divided into six modules: loading data,hash table update,matching lookup and selection,Huffman coding,Huffman code stream packing and compressed stream output.The parallel processing of data compression is achieved by the parallel processing window design.According to the match selection eliminates the relevance of parallel processing.Also between the modules establish multi-level pipeline process structure,and ultimately improve the Gzip compression data throughput.2.The implementation of the Gzip data compression architecture with high throughput is accomplished based on the Vivado-HLS tool.According to the proposed Gzip compression hardware architecture,the compression sub-module is implemented and optimized by HLS tool respectively.According to adding the directive ARRAY_PARTITION,the storage structure of the array could map into registers.According to adding the directive UNROLL, the sequential execution process could map into parallel processing which could shorten the processing time in parallel window structure.Multi-level Implement between modules by adding directive PIPELINE and DATAFLOW.Finally the compression architecture verify by RTL simulation based on the HLS tool.This paper proposes a multi-level parallel processing hardware architecture for Gzip compression hardware implementation and implement based on the Vivado-HLS tool.The experimental results show that the architecture achieves a compress throughput of 3.46 GB / s at a frequency of 227 MHz when the parallel processing window size is 16.Which is 10.4 times higher than the current software by zlib.In addition,the hardware acceleration design architecture provides scale scalability,in which the size of parallel windows grows proportionally to resource size and throughput.In this paper,the proposed Gzip compression architecture with high data throughput,meanwhile can adapt to different sizes of FPGA implementation.