A Design And Implementation Of GZIP Decompression Algorithm Based On The FPGA

In recent years, with the development of science and technology, the computer networks became an indispensable part of people's daily lives. Faced with huge amounts of data need to interact, data transmission and storage requirements becomes very urgent. Compress data before transmission or storage will be more convenient. Data which compressed will need smaller place than the original data, and which need low bandwidth and low transmission quantity and reduce transmit time when we transmit it. So it is necessary before transmission or storage compressed data and decompressed it when we need the data.Traditional we use software for data compression and decompression. But there is a disadvantage with software implementation that is software will occupy plenty of CPU resources when compress or decompress big data. It can reduce CPU processing resource utilization for compression/decompression if using hardware implementation. And now the rapid development of FPGA chips makes its capacity and data processing speed has greatly improved, so using the decompress method based on hardware can improve compression rate, reduce wait time when browsing the Web.For software compression and decompression of consuming large amounts of CPU resources and software for handling big data problems are poor, in the comparative analysis at home and abroad on the basis of a variety of compression algorithms, analyze the strengths and weaknesses of various compression methods, and ultimately selected general real-time lossless compression algorithm that is GZIP algorithm to realize data processing from server to the client. This thesis proposes a GZIP decompression algorithm based on FPGA. Modules involved in the reconstruction of data conditions to improve compression rate. Designs the module in under the realization data restructuring condition, as far as possible enhances the decompression speed. The GZIP compression using the deflate algorithm, decompression using inflate algorithm.Verilog language was used to complete the GZIP decompression hardware design. Take advantage of FPGA parallel processing of data design, accelerating the rate of decompression. By increasing the FIFO module pipeline processing of data, and adding multiple enclosures, to cache large amounts of data, and in the process of building dynamic Huffman trees use more RAM to fully take advantage of FPGA design of parallel, accelerate the establishment of dynamic tree, reducing wait time.This thesis simulated with Questasim and chose different size and different type file for compression mode test, the results of the simulation using MD5 tool to generate the message digest for verification purposes. Compared the files are extracted with uncompressed files the message digest is exactly the same, proved the feasibility of the design. Verification with the FPGA.Data transmitted with DMA core from computer to the FPGA, uses the standard file to test, the decompress processing occupy the single channel throughput rate up to 600 mbps and MD5 checksum tool to extract the message digest, and the message digest of decompressed files is same as the original file, proved the validity of the hardware design. The results of the verification show that the GZIP decompression modules can decompress the file compressed by hardware and software, and the decompression rate increases 40 percent compared to the same period software speed. It lays the foundation for the hardware implementation of the algorithm on the server.