Research And Design Of Fast Locking And Low Jitter Charge Pump Phase Locked Loop

With the development of integrated circuits,integrated degree of chip is getting higher and higher,and also the working frequency of the digital ICs,so the performance of the pll apply in lock recovery circuit,frequency synthesizer,timming skew circuit etc puts forward higher requirements.CPPLL is a mixed-signal phase-locked loop,for its simple structure,zero static phase in theoretically,it is very popular.Therefore,it is important to study how to reduce the phase lock-in time and the output jitter of the CPPLL.The basic working principle of CPPLL and the linear superposition principle of CPPLL’s output jitter were introduced in the thesis first.Next,ways to reduce the output jitter were summarized.The common methods for fast lock were studied too,and an initializing circuit which can reduce the lock time was proposed.The initializing circuit has a simple structure,few transistors and no significant increase in the layout area of the CPPLL.To reduce the loop lock time,a non-linear PFD was adopted,when the input phase difference between π and 2π,the relation between input and output is not linear,the output maintain the maximum value,so it can speed up the loop lock.A better matched CP was designed,and the VCO’s control voltage was set to be half of supply voltage to reduce the effect of the charge pump output voltage on the output current.The fully differential ring oscillator can suppresses common mode noise,so a fully differential ring oscillator was designed to lower output jitter.In order to suppress the fluctuation from power supply,a LDO was designed to supply for the CPPLL.The LDO with enhanced transient current efficiency buffer,can reduce power consumption,enhance the transient response of the LDO,thereby reduce the CPPLL’s power jitter.Through the above methods,a fast lock and low jitter CPPLL was designed and implented in this thesis.Based on the 0.35μm CMOS process,The CPPLL designed in this thesis was verified by spectre simulatior.The CPPLL’s lock time with the proposed initialization circuit is reduced by 45% compared to the CPPLL without the proposed initializing circuit.Therefore,the initialization circuit proposed in this thesis reduce the loop lock time effectively.When VCO frequency is 10 MHz,its phase noise is-115 d Bc/Hz@1MHz,the output RMS peroid jitter of CPPLL is 50 ps.