Design And Implementation Of CPPLL Applied For 6.25Gbps SerDes

With the rapid development of integrated circuits and communications technology,the traditional parallel data transmission is unable to meet the needs of long-distance high-speed data transmission,the serial interface Ser Des is gradually becoming the mainstream of high-speed interface technology.As a core part of SerDes,serializer and clock recovery circuit require accurate clock generation circuit support,the jitter of the clock signal affects the performance of the serializer and clock recovery circuit directly.Ser Des PHY need to meet multiple protocols,different protocols have their corresponding clock frequency,adaptive bandwidth CPPLL become the preferred structure to achieve the performance indicators,the structure not only has low power consumption、easy integration of traditional CPPLL,but also achieve optimal jitter of different frequency output.The design uses 65 nm CMOS technology,as a clock generation circuit applied for6.25 Gbps SerDes design.Reference clock 125 MHz,at 10-12 BER conditions,the total phase jitter of less than 7.5 percent.At circuit design,PFD dead zone is improved to improve the phase accuracy;At CP circuit,by taking specific measures to non-ideal factors of traditional CP,spurious output can reduce 13.8dB than conventional CP;In order to achieve low phase noise frequency output,CP uses dual structure to achieve CP adaptive bandwidth,On the basis of the classical differential structure,VCO circuit is not only adjusted to achieve output duty cycle is 48 percent to 52 percent,but also the capture range can reach from400 MHz to 5GHz;High-speed latch structure is used to feedback divider,which allows that a 4.6GHz input signal can still normal divider;Phase-locked loop circuit also used the accelerated start,which can lock quickly.Power consumption is less than 29 mW at ambient temperature and pressure,the total jitter is less than 7.5 percent,chip layout area is 0.29mm~2.