Research Of Efficient Pulse Compression System Based On FPGA

In traditional radar signal processing mechanism,the whole imaging algorithm including pulse compression is realized in DSP.However,limited to its memory,DSP can’t complete the algorithm alone with mass processing data and the DSP’s real-time character is also bad in this condition because of its sequential processing mechanism.According to the characteristics of multiple working modes and mass data processing in the modern radar system,an effient pulse compression system consist of signal sampling,preprocessing and pulse compression based on FPGA is proposed.Firstly,basic principle of signal sampling is introduced to illustrate the condition in which anolog signal can recover from the sample data.Quantization error is also analysed and the relationship between ENOB and SNR is given in ideal condition.To support performance test,the physical meaning and calculating method of important performance data are presented.The function,architecture and calibration method of EV10AQ190 A type ADC are introduced and test results show that its ENOB is better than 7.7 and its SFDR is above 45 dB.Secondly,in order to reflect the advantage of polyphase filter structure,its mathematic expression and physical structure are deduced and presented in detail.Based on the theory analysis above,polyphase filter structure is used for digital quadrature down-convert to improve filter structure and processing efficiency.In this papar,software simulation and hardware test are involved in polyphase filter structure’s design,the test results show that the design can meet the requirement of anit-alias filtering,slowing data rate and decreasing data mass both in design and practice.Thirdly,aiming at the core function of the system,an efficient frequency-domain pulse compression approach based on FPGA is proposed.In this approach,FFT module is realized by a compound FFT architecture whose computing power is two times of radix-4 Burst IO architecture’s and reference signal is timely created by LUT method depending on basic parameters of transmitted signal.The simulation results based on Matlab and ISE platform show that with the proposed method 32768 points range compression can be efficiently realized with excellent real-time character and the processing time is less than the half of time that TMS320C6678 DSP costs in the same transform points.In addition,the processing results of the method can meet the requirement of engineering practice.Finally,the pulse compression module is encapsulated as IP core and the whole pulse compression system is tested on the hardware test platform using Virtex-7 FPGA as its core processor.The results show that the system can realize multiple working modes pulse compression with good performance and it is of grate value for small size radar signal processor based on pulse compression machanism.