Design And Implementation Of Convolution Neural Network System Based On FPGA

Convolutional Neural Network(CNN)is a typical multi-layer neural network,which is the first structural model to successfully train multiple hierarchical networks.Its weight-sharing network structure makes it important in Processing and speech recognition.CNN algorithm is usually in the CPU or GPU software to achieve the way,this method is simple but cannot play the characteristics of CNN parallelism,and training speed is slow.FPGA is rich in computing resources,SRAM structure based on the FPGA in the FPGA operation of the on-chip resources to be reconfigured to achieve the system logic switching,improve system flexibility and resource utilization.This paper presents a method of implementing CNN by dynamic reconfiguration of FPGA.This paper first introduces the reconfiguration method,configuration technology and implementation flow of dynamic reconfigurable technology based on FPGA,and establishes the appropriate reconfiguration scheme according to the CNN algorithm.The CNN model,network structure and activation function are briefly introduced and analyzed,and the possible problems of CNN implementation are analyzed and the corresponding solutions are put forward.The reconfiguration and parallelism of CNN are analyzed,the CNN training process is divided into four different stages,including the initialization phase,forward propagation phase,reverse propagation phase and weight update phase.This paper designs a convolution neural network algorithm with relatively simple network structure and low weight,called My Net algorithm,and realizes the dynamic reconfigurable system based on FPGA based on the forward propagation module of My Net algorithm.The forward propagation phase of the My Net algorithm is divided into three different sub-modules: the convolution sub-module,the sub-sampling sub-module and the fully-connected sub-module.The convolutional sub-module and the sub-sampling sub-module are mainly analyzed,and the convolution operation and the sub-sampling operation are analyzed in detail.A concrete implementation method is proposed.A sequential control strategy is proposed to ensure the sequential execution between modules.The various modules of the system are realized based on Verilog HDL.The My Net algorithm is implemented and tested on the CPU,and compared with the performance of the Lenet-5 algorithm,which confirms its good training speed and better performance.The modules of the system are tested separately to verify the function of the module.Taking the arbitrary module as an example,the timing control strategy of the system is tested.Finally,the whole system is tested and the correctness of the system is verified.