On-chip ESD Protection Design Of High Speed Interface

In recent years,with the rapid development of information technology,a variety of new electronic devices are invented incessantly.The signal transmission also requires higher and higher transmission rates due to the increase of data volume,which means that as the semiconductor technology is getting more advanced,chip is getting smaller and weaker,electrostatic protection is particularly important;it not only requires strong protection features,but also need to minimize the parasitic parameters,so as to minimize the impact of signal transimission of the entire high-speed interface circuit.In this paper,focusing on the actual failure cases of three different high-speed interface chip:multimedia chip,USB Type-C interface chip,failure analysis,anatomy and reverse design are made to find the main weak part of the chip and a new device are proposed to ensure that the ability of discharging current of the device while reducing the device area.Then some cases of EOS failure are analyzed and the main EOS protection measures are summarized.Moreover,a collaborative simulation protection scheme is proposed.The main research contents are as follows:1.Aiming at the problem of ESD failure encountered in the practical use of a multimedia interface chip-VBO interface chip,a detailed analysis is carried out.In view of the poor robustness of the protection device,the large area of the device and the improper protective window,a new protective device is designed and typed out in 28 nm CMOS process to meet the needs of the actual circuit.By the test-verification,it not only ensures the robustness of the device,significantly reduce the device area,but also meet the actual needs.2.Conduct comprehensive ESD performance tests on two USB 3.1 Type-C interface chips used on mobile phones,including TLP test,failure analysis,anatomy and reverse engineering,etc.At the same time,conduct a comprehensive summary and comparison of ESD protection methods of these two chips.3.Several EOS failure cases were analyzed and several common EOS protection schemes were summarized.A new TVS protection device was also proposed in 0.18μm CMOS process for EOS protection while TVS are commonly used in the industry.TLP tests were conducted to verify the ESD performance of the new TVS structure.At the same time,a collaborative simulation method of on-chip protection and off-chip protection is proposed,and its validity is verified through several cases.