Microprocessor Pipeline Design Based On MIPS32 Architecture

With the rapid development of Internet technology,a variety of electronic devices developed by embedded microprocessor system have become popular among people.Also,it has occupied more and more markets because of the advantages of high performance,low power consumption and portability.As a key factor affecting the performance of the processor,the design and optimization of the pipeline are very important.The reduced instruction set computer(RISC)which has a great influence on the development of the microprocessor,has been widely applied to the design of the processor architecture owing to its advantages of the simple instructions and addressing mode since it was proposed in the 1980s.Moreover,because of these advantages,it is more convenient for the instructions to be operated in the pipeline.The MIPS32 architecture which is developed by MIPS company,is undoubtedly a classic pipeline processor architecture with all the advantages of RISC.On the basis of mips32 architecture research,This paper realized the design of microprocessor five stage pipeline structure,whose goal is to make most of the commands completely executed in one clock cycle.Only by the instruction of division,the multiplication accumulator and the regressive instruction execution requires multiple clock cycles,can you make the treatment of pipeline to a maximum efficiency.This paper will detail the MIPS architecture instruction set,register stack,Cache design and the exception handling and so on.On the basis of the analysis and research on data,structure,control and other issues on every stage of microprocessor design functional requirements and execution,this paper has a detailed module classification on the five stages of pipeline.Finally,we use the Hardware Description Language Verilog code to implement each module to have specific functions.The five level pipeline to be achieved in this design contains the five stages of fetch,decode,execute,memory access and write back.Fetch stage will remove the need to enter the pipeline execution of instructions from the instruction memory.This phase of the design of PC module will give the address of the current instruction,and can determine the specific address of the next instruction according to the control signal.IF/ID register module is a stored information instruction pipeline register.Decoding stage needs decoding analysis on the removed instruction information and needs to file out source operand from the register and transfer instructions of the jump address;so decoding stage designs instruction decoding and the metastasis of ID module and is used to store data Regfile module ID/EX register module.The register ID/EX is to store all kinds of information collected on decoding stage.Execution stage of all kinds of data from the decoding is performed by computing the correlation.This phase of the design includes ex module,div module and EX/MEM register module.Most of the operations needed to be performed will be completed in the Alu operation unit of the ex module.Div module dedicates to a division operation.The execution after the completion of the various types of data will be stored in the pipeline registers-EX/MEM.Visit deposit stage of memory access instructions and exception processing,and the execution of these instructions will occur in the MEM module.RAM module is used to store data,the memory stage results will be stored in the MEM/WB register.Write back stage designs four modules,among which the co-processor CPO module is used to control the abnormal situation.LLbit register module is a special register module that is required when executing LL and SC instruction.Hilo register module is used for storing multiplication instruction results.Ctrl module generates a control signal which is to achieve suspension,removal and other functions on pipeline.In the end,we use the Mentor simulation software Modelsim to simulate the function of each module,and compare the simulated results with the expected results.If people get the correct results,it just shows the correctness of the design.