Clock Tree Optimazation And Design For Manufacture In A 0.13?m Cmos Core

With the rapid development of integrated circuit technology,the rapid increase of the scale and design complexity of digital circuits,bring new challenges to the timing and manufacturability of digital backend physical design.On the one hand,searching for a fast and effective clock tree synthesis method to solve the problem of timing closure,has become necessary for high performance digital circuit design.On the other hand,the issue of chip yield drop caused by the manufacturability factors in deep submicron and nanometer process is considered much in the backend design.Determining the appropriate design flow with DFM(Design For Manufacture)to eliminate the deviation between design and production is essentially important for physical design.In this thesis,the physical design and implementation of a 0.13?m communication chip is presented,the clock tree synthesis and manufacturability design are especially focused.Based on the basic theory of clock tree synthesis,a manual optimized method with setting ignore pin is adopted to solve setup violation,and optimizes the time slack by clock tree network ECO(Engineer Change Order).According to the theory of design manufacturability,for the possible problems including CMOS latch effect,open metal interconnect and antenna effect,the methods with the tap cells insertion,double via insertion and antenna diode added are adopted to improve the manufacturability of the chip.Furthermore,the design flow with DFM is proposed with the above approaches.The physical design of the communication chip is completed in SMIC 0.13?m technology.Clock tree synthesis methods are adopted to optimize timing,which increase setup slack from 0.20 ns to 2.31.The manufacturability design process is used to improve design manufacturability: the antenna effect with top layer in the layout is eliminated completely,the interconnected metal wire is optimized and the insertion rate is 80.90 %,the critical area and the density uniformity of layout are improved in different degrees.Finally the setup time slack is 0.89 ns,the hold time slack is 0.28 ns,achieving the design goal of timing closure.The chip is taped out successfully and completed the test.