Design And Implementation Of A FPGA-based Low-voltage Broadband Powerline Channel Emulator

Today,Powerline communications attractive world with development prospects and potential market value,become a hot research field for many scientific research institutions and companies.In recent years,in the context of a series of concepts put forward,such as energy information,smart grid,Internet of things,energy Internet and so on,the development of power line communication also been put to a new level.With the gradual maturity of power line communication technology,its related products become more and more complex,the proportion of the system testing in the whole product development process is growing.In order to save manpower,resources and shorten the development cycle,avoid a large number of off-site repeated,time-consuming test experiments,channel simulator has become an inevitable demand.Based on the Xilinx FPGA System Generator platform,this paper designs and implements a low-voltage broadband power line channel simulator,which can easily generate the channel test environment of various requirements to meet the power line development process and product performance testing needs.Firstly,the general characteristics of low voltage power line communication are analyzed in detail,and the influence on the transmission channel is described from the aspects of multipath channel and noise.The low-voltage power line multipath channel introduces the classical multipath channel model and the two-port model based on the transmission line theory.The noise analysis uses the widely accepted Middleton Class-A model to generate impulse noise,while the burst noise is generated using the improved twoorder hierarchical Markov chain model,which is the first time to be modeled with a specific envelope Morphological noise.Secondly,the background noise,narrowband noise,periodic frequency impulse with synchronous frequency and asynchronous frequency are introduced,and the corresponding reference model is given.Then the hardware implementation method of multipath channel,random impulse noise and burst noise is presented.A more reasonable scheme is obtained after weighing comprehensively by comparing and analyzing the advantages and disadvantages of FIR and IIR filters,and evaluating the influence of different parameters on hardware resource usage under the same reference channel and the root mean square error of the transmission function curve under different order of the filter.The classical Middleton Class-A impulse noise model is studied,and the implementation method is proposed for the first time in the case of only theoretical analysis.The implementation of burst noise is introduced,and the realization process of key modules such as the principle of the pseudo-random number generator,the state space division and the state transfer matrix storage access in ROM is introduced,and the suitable scheme for hardware implementation is given.Finally,this paper used the advanced tools provided by Xilinx FPGA,the channel simulator is implemented on the KC705 evaluation board.Through the verification and analysis of each sub-module,the accuracy of PLC channel simulator is proved.