FPGA Implementation Of CA-SCL Decode Algorithm Of Polar Codes

The Polar codes are the family of Error Correction Codes constructed on the basis of channel polarization which achieve the symmetry capacity for any binary input discrete memoryless channel(BDMC).Due to its significant characteristics,Polar codes has become a coding scheme for 5G enhanced mobile broadband scene control channels.although there are a large number of researches on Polar codes,many of them still remain on Polar codes theory research.There are few researches on their practical applications,especially on hardware implementation.Therefore,Polar codes are studied from three aspects: codes construction,decoding algorithm and hardware implementation in this paper.Accurately constructing the Polar code according to the polarization channel condition is the key to guaranteed its performance.In this paper,we first use the Gaussian approximation and the simplified Bhattacharyya method to construct the Polar codes.Then we propose a Polarcodes adaptive construction method based on channel,which optimize the construction of Polar codes and make their performance fully utilized.Secondly we study the decoding algorithms of Polar codes including SC,SCL and CA-SCL algorithm.What is more,we also build a Polar codes algorithm simulation system through which the simulation and performance comparison of different decoding algorithms are given.Successive-Cancellation(SC)decoding algorithm has the advantage of low complexity but do not perform well in short codes.The improved Successive-Cancellation List(SCL)algorithm based on the SC algorithm preserves multiple decoding paths,improves the fault tolerance of the decoding algorithm,and improves the performance of the Polar codes.The CRC-assistant SCL(CRC-Asistant SCL,CA-SCL)algorithm improves the path selection criteria,which further improves the performance,and makes Polar codes achieve better performance than the Low Density Parity Check(LDPC)codes.In addition,this article also focuses on the hardware implementation of Polar code decoder.SC algorithm,the basis of SCL and CA-SCL,is the core decoding algorithm of Polar codes.The recursive structure of SC algorithm makes it very suitable for hardware implementation.Therefore,this article focuses on the several hardware architectures of SC algorithm,including FFT architecture,tree architecture,linear architecture,and vector overlap architecture.The tree architecture and the line architecture reduce the hardware complexity through hardware resource multiplexing,while the vector overlap architecture utilizes the idle processing elements to process multiple vectors in parallel,thereby improving the throughput of the decoder.In addition,this paper proposes a hardware architecture based on semi-parallel processing method,through which the decoding code length of the decoder can be changed at the cost of very small throughput.At the end of this paper,the FPGA(Field-Programmable Gate Array)architecture of CA-SCL decoder is designed based on the tree architecture.The hardware implementation of the decoder is introduced in detail,and the FPGA implementation of CA-SCL decoder is completed.