Satellite Receiver Baseband Communication System Design

Software defined radio technology can make the satellite communication system’s modulation and demodulation mode,multiple address mode,encode type and so on switch more flexible,and keep on optimizing and improving the system’s performance.With the rapid progress of wireless communication,satellite communication system goes to the multi-standard era,and the birth of software defined radio solves the compatibility problem between different standard satellite communication systems.The generation of software defined radio,of course,makes sense for satellite communication system,but the demand becomes more complex in the real project,which leads to the increasing use of resources.Later,the dynamic reconfigurable technology based on FPGA comes out,aims at improving the efficiency of resource utilization and using small-scale FPGA chip to achieve the system with more features and space.Dynamic partial reconfiguration technology makes the software defined radio system’s development cycle shorter,the resource budget more economical and the design more flexible.Based on the software defined radio theory and dynamic reconfigurable theory,this paper designs and implements software defined radio baseband communication system.On this basis,the related hardware platform is designed and manufactured,which can implement the dynamic reconfigurable function of some modules in the software defined radio and realize the partial dynamic reconfiguration process.The research contents mainly include the realization of software defined radio algorithm,the production of hardware platform which makes FPGA the main chip,and use dynamic partial reconfiguration to switch two ways of modulation and demodulation methods and so on.Finally,it is proved that the combination of partial dynamic configuration and software defined radio will make the software defined radio communication system more resource-saving and flexible by comparing the resource utilization of the system which makes the two system in one FPGA with the resource utilization of the system when we achieve the partial dynamic reconfiguration.