On-chip Network Fault Tolerance Technology Research

With the development of the integrated circuit,traditional System-on-chip(SoC)based on the bus interconnection must face three main problems:the scalability problem caused by the limit address space,communication efficiency problem,area and power consummation problem attribute to the global synchronization.Interconnection network-on-chip(NoC)thorough settlement these problems architecturally.NoC must be the mainstream technology of the next generation integrated circuit product.However,with shrinking silicon size,NoC will be susceptible to the crosstalk,electromagnetic interference,and high energy particle,hence make more errors.As the communication node in the NoC,router is the most important component.The router is responsible for receiving and forwarding the packets.The router with soft error will impact the overall performance of the SoC.Based on the soft error in the router,this paper do some jobs appear below:Firstly,this paper analyze the Nirgam simulation experiment platform.Add the soft error injection module,triple module redundancy,the statistics module of the reliability and throughput.Secondly,this paper analyze the soft error in the packet,especially for the head flit,data flit and tail flit.Summarize the reasons and the location of the soft error.We also do the simulation experiments for the relationship between the number of error and throughput.The result shows the throughput is lower and lower with the number of soft error increasing.Furthermore,the soft error in tail flit is more serious to the throughput.Besides,we also simulate the relationship between the number of virtual channel and throughput.The result shows that the more virtual channel do not mean the higher throughput.At last,we design and realize the fault tolerant scheme based on the macro virtual channel in the basis of the analysis of internal router error and virtual channel.we design and realize the fault tolerant scheme based on the virtual channel.Do the fault-tolerant processing for the different kind of the packets on the NoC.Then we do a lot of simulation experiments.Then we design the relevant fault-tolerant router structure and the control strategy of virtual channel allocator.In the Nirgam simulation platform,we do lots of simulation experiments for the proposed fault tolerant schemes in the different error rate(high error rate,medium error rate and low error rate).The result shows that the correct packets rate is above 99.99%in the high error rate(le-3)and medium error rate(le-4～le-5);the correct packets rate is more than 99.999%in the low error rate(le-3).The fault tolerant scheme presented in this paper can protect the packet transmission in the NoC and ensure the reliability of the chip.