Design Of Host Interface Unit Based On ZYNQ

In recent decades,China's economy has developed rapidly,and the demand for mineral resources has been continuously increasing.However,in our vast territory,there are still a large number of mineral resources that have not been identified.Geophysical exploration techniques can be used to detect the structure and structure of the Earth's interior to find resources.Transient electromagnetic method is a very important method for geophysical exploration.Its basic principle is to use the law of electromagnetic induction to detect the resistivity of the medium.The multi-channel transient electromagnetic method multi-channel transient electromagnetic expansion,which brings new challenges to the data transmission system.The multi-channel transient electromagnetic data transmission system consists of a data center and subordinate distributed nodes.In order for the data center to communicate with subordinate nodes,a specific peripheral device namely Host Interface Unit is required.This paper introduces the design and optimization of Host Interface Unit in multi-channel transient electromagnetic data transmission system.The multi-channel transient electromagnetic data transmission system is divided into four layers in structure,corresponding to four kinds of stations,which are Data Acquisition Unit,Battery Management Unit,Line Management Unit,and Data center.Multiple chain structures are cascaded between stations.The data transmission system features scalability and reliability.The reliability of system data transmission is achieved through TCP/IP protocol and HardwareReliable Data Transmission Protocol.The data transmission system puts forward the following requirements for the Host Interface Unit:high data rate,reliability,portability,system management.The design of the Host Interface Unit is based on the Xilinx ZYNQ,which contains the FPGA part and the ARM part.The design of this paper is the collaborative design of the FPGA,the driver,and the application program.The Host Interface Unit uses Gigabit Ethernet to implement hardware-based reliable transmission protocols and data transmission at the Line Management Unit on the FPGA.The data transmission between the Host Interface Unit and the Data Center is also via Gigabit Ethernet,but the reliability of the data is ensured by the TCP protocol on the ARM.Communication between FPGA and ARM is realized through high-speed DMA transmission technology.This paper also improves the data rate by packing and merging data frames,and improves the reliability of data through the design of multi-level caches.The data rate test shows that the data rate of the Host Interface Unit can reach 330Mbps,which meets the requirement of high data rate.This paper also proposes an optimization scheme to increase the data rate of the Host Interface Unit,which is based on an asymmetric multiprocessing architecture and the LWIP protocol stack.The reliable data rate of this solution has been tested to 530 Mbps,a 60%improvement over 330 Mbps.