Design Of Low Power Low Noise Chopper Amplifier Chip For Neural Signal Acquisition

Recently,Microelectronics technology in biomedical application has been developing and the interdiscipline of biomedical electronics has thus gained greater attention from academia.In some critical application such as bio-signal recording,brain-machine interface,the size,power consumption,and noise performance of signal acquisition devices are strictly constrained.The analog front-end amplifier aroused great attention from researchers,as it is a crucial module of the bio-signal recording system that decides the performance of the whole system.So far,low power,low noise,high input impedance,high common-mode rejection ratio,high power source rejection ratio,and small chip area are the main concerns in analog frontend amplifier circuit design.This thesis focuses on investigation,analysis and design of the front-end amplifier circuit applied to the implanted multichannel neural signal recording system.The main works include:(1)Regarding the application scenario of implantable multichannel neural signal recording,the performance requirement is discussed from the perspective of the system level.Based on capacitive-coupled close loop topology,chopper stabilized technique was implemented in the multi-channel amplifier system,which is composed of two-stage amplifying circuits and chopper switches.(2)To meet the requirement of low-power and low-noise performances in implantable devices,a novel inverter-stacking current-reuse topology was proposed based on existing currentreuse techniques.A four-channel neural signal recording front-end amplifier chip with characteristics of low complexity and low noise efficiency factor was realized based on a four-inverter stacking.Using 0.18?m UMC process to design the proposed front-end amplifier chip with novel inverter-stacking current-reuse topology,the simulation result indicates that the proposed amplifier consumes a total current of 198 n A in a 1.8V supply,shows a bandwidth of 5.41 k Hz,input-referred noise spectrum density of 76.6n V/?Hz and gain of 25.6d B.The noise efficiency factor and power efficiency factor are therefore calculated to be 0.888 and 1.419 respectively.In addition,the proposed inverter-stacking topology cancels the current recombination circuitry,exhibits a high inter-channel rejection ratio and linear-increasing number of output branches,which enables a next-generation multichannel neural signal recording amplifier topology that compatible of realizing ultra-low noise efficiency factor.