Research On The Key Technologies Of Multi-channel Low-power EEG Interface Chip

With the rapid development of integrated circuit technology and Internet of Medical Things(IoMT),low-power and high-accuracy electroencephalogram(EEG)interface chips have been widely used.The judgment of brain health status can be easily realized through the accurate and timely collection,analysis,and processing of human EEG signals by portable EEG interface equipment.To meet the requirements of the EEG acquisition quality and the service time of portable EEG interface equipment,EEG interface chip not only needs to have the characteristics of multi-channel signal acquisition,low system noise,and high quantization accuracy,but also needs to be designed with ultra-low power consumption to prolong the service life of the equipment under limited supply power.Multi-channel EEG acquisition can be realized by parallel multi-channel circuits,but the power consumption and area of the chip increase significantly,resulting in a rapid increase in acquisition cost.Current-reuse is a new technology of multi-channel EEG acquisition,which can realize low average power consumption by multiplexing static bias currents of multi-channel circuits.Therefore,this technology can realize the characteristic of low power consumption on the premise of ensuring multi-channel high-quality EEG acquisition.At the same time,to realize the digital quantization of EEG signals,the design of high accuracy and low power analog-to-digital converter(ADC)is needed.The successive approximation analog-to-digital converter(SAR ADC)is fast and consumes low power,making it suitable for EEG interface chips.However,the drawbacks of comparator noise and rapid increase in chip area with conversion bits limit its resolution improvement.Noise-shaping SAR ADC integrates noise-shaping technology of Sigma-Delta ADC into SAR ADC and achieves high conversion accuracy and energy efficiency,which is suitable for EEG interface chips.Firstly,the characteristics of EEG and the basic structure of analog front-end(AFE)circuit are studied,the principles of key circuits are introduced in detail,and the low-noise and lowpower circuit design technologies are discussed.Then the structural characteristics and performance indicators of typical ADC are elaborated,and the detailed analysis was conducted on the characteristics of noise-shaping technology and noise-shaping SAR ADC.Based on 65 nm standard CMOS process,this dissertation proposed and implemented a lowpower and low-noise current-reuse biological AFE(Bio-AFE)chip for multi-channel EEG acquisition.A new low-power orthogonal recombination method is proposed in the fourchannel current-reuse amplifier,which reduces the recombination current by half and cuts down the power supply voltage while ensuring the crosstalk suppression capability,resulting in a lower average channel power consumption.A four-order current-cancellation subthreshold-source-follower low-pass filter(CS-LPF)is proposed in this dissertation,which realizes the reduction of the chip area and power consumption by cross-coupling current cancellation technology.The core area of the proposed chip is 1.17 mm× 0.82 mm.Based on 65 nm standard CMOS process,a dynamic-comparator-reuse noise-shaping SAR ADC(DN SAR ADC)is designed and implemented in this dissertation.Based on the proposed all-in-one dynamic comparator/ dynamic amplifier(ADD),a second-order dynamic-comparator-reuse noise-shaping(DN)technology is proposed to effectively reduce the additional capacitance area and it achieves a good compromise between conversion accuracy and power consumption.The proposed ADD can perform the functions of dynamic comparison and dynamic amplification in different phases of the same conversion cycle,avoiding the design of two additional dynamic amplifiers,simplifying the circuit structure and reducing the chip area.The core area of the proposed chip is 0.68 mm× 0.19 mm.This dissertation implements and measures the two proposed chips,and then conducts EEG measurements on the system composed of two cascaded chips.The measured results show that the proposedBio-AFE has a variable gain of 40.5-56 dB.The fully differential LPF with a power consumption of only 4.8 n W achieves 50% capacitance reduction.The average power consumption per channel of the proposedBio-AFE is only 2.6 μW,and the noise efficiency factor(NEF)and power efficiency factor(PEF)are 1.81 and 3.93 respectively.When the sampling rate is 10 k S/s,the proposed DN SAR ADC consumes 0.1 μW power consumption at a supply of 1 V.The proposed second-order DN SAR ADC achieves a SNDR of 74.78 dB,a Fo Ms of 167.8 dB,and a Fo Mw of 56 f J/conv.-step within 200 Hz biological signal bandwidth.The measured results of the cascaded system show that the proposed multi-channel low-power EEG interface chip system can collect four channels of EEG signals and complete analog-to-digital conversion of the signals.