Design Of High Resolution Time Measurement Chip Of Electromagnetic Calorimeter Based On SCA

The heavy ion superconducting synchrotron(NICA)and its multifunctional detector(MPD),which are being built at the Joint Nuclear Research Institute(JINR)in Dubna,Russia,are mainly used to study quark-gluon plasma with high baryon density.The energy is between high and low energy regions.The NICA/MPD detector is designed with a high-efficiency electromagnetic calorimeter(ECal)system to accurately measure and identify the photon,electron,lepton pair and neutral meson generated in the reaction of heavy ions.In order to improve the ability to identify these particles,The time measurement resolution of ECal must be improved.Based on this goal,this paper designs a switched capacitor array(Switched Capacitor Arrays,SCAs)type waveform sampling chip to measure the time of the ECal detector with high precision.The main research contents are:A 4-channel high-speed waveform sampling chip based on a switched capacitor array is designed.Each channel is composed of a sample-and-hold circuit,a sampling clock generation circuit,and a readout control circuit.The sample-and-hold circuit consists of 256 sampling switches and sampling capacitors.composition.The sampling switch selects the structure of the transmission gate and the virtual tube to reduce the influence of channel charge injection and clock feedthrough.By optimizing the size of the N-type and P-type transistors that constitute the transmission gate,the on-resistance of the entire input dynamic range is uniform Smaller.Sampling capacitors use MOS tube capacitors to reduce chip area and improve chip integration.The sampling clock generation circuit is composed of a delay-locked loop(DLL)and a pulse width adjustment circuit,and the main units of the DLL circuit are a voltage-controlled delay chain,a phase detector,a charge pump,a loop filter,and Start the circuit.The readout control circuit is composed of a source follower and a shift register to realize the serialized output of the sampling signal.The layout uses shielding technology and a method of increasing the line width to reduce the parasitic resistance and capacitance of the trace,thereby increasing the analog input bandwidth.The overall chip layout parameters were extracted and verified by simulation.The simulation results show that the sampling rate of the chip is adjustable in the high-speed range of 800M-2Gsps,the transient average power consumption is 0.24mW,the input dynamic range is 500mV,and the time resolution is 63.76ps.The chip area is 2.97mm x 1.5mm.The test system of the chip is designed.The system is composed of a chip binding board,a motherboard,an AD sampling board,and a HPDAQmini data acquisition board.The binding board is used to bind the chip pins,filter and reduce noise on the power supply,and output 4 channels of analog signals.The binding board uses PCIE plug-in to connect with the motherboard;the HPDAQmini board realizes the basic configuration of the chip and the function of data sampling and transmission.The preliminary test results of the chip show that the chip achieves high-speed sampling,and the system noise and time measurement accuracy meet the design requirements.