Digital Output Magnetic Resistance Sensor Interface ASIC Chip Design

As an emerging type of materials,tunneling magnetic resistive(TMR)sensors,have the advantages of high dynamic range and high magnetic field sensitivity compared to Hall sensors,flux gates and traditional Solid-state magnetoresistive sensors,which are now widely used in various fields.However,due to the low output frequency,small amplitude and the remarked temperature drift of the tunneling magnetic resistive sensor,the research and design of the tunneling magnetic resistive sensor interface ASIC circuit is of great significance to the future development of the tunneling magnetic resistive sensor.The interface circuit of the digital output magnetoresistive sensor designed in this paper mainly includes the Sigma-Detla ADC post-stage digital decimation filter,digital temperature compensation circuit,and the low-noise and low-offset instrumentation amplifier of the pre-stage analog detection.Based on the characteristics of the output signal of the tunneling magnetic resistive sensor with low frequency and large noise,this paper has designed a specialized instrumentation amplifier characterized by low noise and offset.The pre-stage signal detection circuit uses a current feedback instrumentation amplifier structure to achieve high input impedance;by discussesing the causes of noise and offset in the circuit,it is suppressed and eliminated based on the chopping technology;this article has designed a ripple suppression circuit to suppress the output ripple signal.The equivalent input noise density of the front-stage detection circuit of this structure reaches 11.72 n V/sqrt(Hz)and it can effectively suppress the output ripple below 10 m V.This article adopts Sigma-Detla ADC to achieve digital output.This topic is mainly aim to design and improve the Sigma-Detla ADC post-stage digital decimation filter.The decimation filter selects a three-stage cascade structure of CIC(Cascaded integratorcomb)-CIC compensation-low-pass filter.The first stage uses a 5-order CIC structure to achieve high magnification extraction;the second stage is devoted to compensate the passband attenuation caused by the first one and the third stage make use of a traditional FIR low pass filter to reduce the transition band bandwidth.The latter two stages simultaneously achieve low-power downsampling,and use two-phase decomposition,CSD(Canonic Signed-Digit)encoding,decimation filter replacement and other technologies to reduce chip size and power consumption.Using Verilog language to realize the circuit-level design of the post-stage digital filter,and the back-end layout design is implemented.In addition,the filter output signal is 24 bit,and the layout area is 2.4×2.4 mm~2.The signal-to-noise ratio(SNR)of the simulated output signal after the circuit is basically the same as the SNR the ideal excitation,and the signal extraction and filtering function is realized.Based on the analysis of the temperature characteristics of the tunneling magnetoresistive structure,based on the relationship between the zero and sensitivity drift of the TMR sensor and temperature,the least squares method is used to fit the polynomial model to achieve temperature compensation.In this paper,HDL hardware description language is adopted to realize the on-chip temperature compensation circuit,and the SPI interface circuit is chosen to realize the parameter and signal transmission.At the same time,the back-end layout design of the overall module is completed,and the generated layout area is 2.4×2.4 mm~2.The temperature compensation circuit can complete the temperature compensation function in real time,effectively solving the temperature drift problem of the TMR sensor.