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Contol Loop Design For High Speed Converter Based On NSGA-?

Posted on:2019-05-06Degree:MasterType:Thesis
Country:ChinaCandidate:M F XieFull Text:PDF
GTID:2382330596960772Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As the development of the power converter is heading to higher frequency,the digital control delay takes a large part in the cycle and the switching loss becomes severe.In order to achieve each cycle control,we need to speed up the procedure of digital control.At the same time,in order to achieve high efficiency,it is feasible to use intelligent optimization algorithms to collect the run-time data and optimize the control parameters at run-time then finally optimized the system efficiency.In this dissertation,the cascade converter is based on Buck converter and LLC resonant converter.A high efficiency and high speed algorithm based on the cascade converter is proposed in this dissertation.Firstly,A PID(Proportion integral derivative)closed-loop controller based on the LUT(Look Up Table)is illustrated.By using the spare store space in the micro controller to speed up the processing procedure,and finally shorten one large part of the digital control delay: the floating point processing time.Secondly,the multi-object optimization algorithm is used to optimize the front-end converter's switching frequency and the back-end converter's switching dead-time.And also write the evaluation function and set up the limitation of the parameters to be optimized in order to prevent detuning.In the system,the coordinate module to let the system optimized the efficiency and stabilize the output voltage at the same time is also introduced.At last,the control algorithm proposed in this dissertation is simulated and verified in the Matlab and Saber by setting up simulation modal,and tested in a 120 w power converter prototype at last.The test result of the prototype showed that,when the output voltage is set to 12 V.The algorithm shortens 75% of the floating point processing comparing to using the calculating PID controller.When the load changed from 10% to 90%,the average settling time is 9ms,when changed from 90% load to 10% load,the average settling time is 12 ms.The efficiency in all load range raised about 5%.
Keywords/Search Tags:Look-up table, Real-time efficiency optimization, Genetic algorithm, Dynamic response
PDF Full Text Request
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