Analysis And Design Of Instrumentation Amplifier For ECG Signal Acquisition

With the rapid development of Internet of Things(IoT),new trends are gradually emerging.The IoT medical devices represented by ECG signal acquisition can be widely used in pediatric and elderly care,chronic diseases management and personal health management.These portable devices can monitor people's daily activities in real time,and compare them with accumulated databases to detect abnormal health conditions for preventive health care.Portable biomedical monitoring devices will be widely used in the near future.For ECG signal monitoring equipment,it is important to provide a highquality signal detection module.The higher the signal quality,the higher the reliability of health information.Therefore,the instrumentation amplifier(IA),which plays the role of amplification,is undoubtedly the most critical module.For better ECG acquisition,the designed IA should provide sufficient gain and a high common-mode rejection ratio(CMRR)while eliminating unwanted offset and 1/f noise.Therefore,in view of the main challenges faced by IA design,based on the accurate acquisition of target signals,a high-common-mode rejection ratio current feedback instrumentation amplifier(CFIA)is designed based on TSMC 0.18 ?m CMOS process.The folded cascode structure effectively increases the common mode rejection ratio.In the circuit,a small Gm-C high-pass filter based on current division(CD)technology is used to set the high-pass filter pole to achieve the purpose of isolating human lowfrequency noise and suppressing DC offset.The post-simulation results show that the circuit consumes 98?W at 1.8V supply voltage and achieves a gain of 35.55 dB from 0.2Hz to 200 Hz.The common mode rejection ratio is 117.4 dB,the input reference noise is 222.3 nV/ Hz(202 Hz),and the in-band equivalent input integrated noise is 6.3?V.In order to achieve better noise performance and further reduce power consumption,a low noise chopper instrumentation amplifier is designed.The circuit uses a folded cascode current feedback structure with Miller compensation.Achieving a high commonmode rejection ratio,a two-stage chopping structure significantly reduces 1/f noise and dc offset,and a second-order Sallen-Key low-pass filter eliminates the output ripple introduced by the chopper switch.The circuit is designed in SMIC 0.13?m CMOS process and consumes 44?A at 1.2V supply voltage.The simulation results show that the input reference noise power spectral density(PSD)is 63.89nV/ Hz and the common mode rejection ratio is 93 dB,noise efficiency factor(NEF)is 8.1.