Parallel Architecture Of Digital Signal Frequency Domain Processing Design

The traditional spectrum analyzer can hardly cope with the increasingly complex signal detection environment.The Real-Time Spectrum Analyzer(RTSA)solves the problem of capturing and analyzing instantaneous mutation signals.RTSA can analyze signals in time,frequency and modulation domains.In the face of rising demand for signal detection analysis,how to improve the ability of RTSA of real-time data analysis,and how to promote for short instantaneous signal capture and analysis ability,gradually become the focus of the attention and research.With real-time spectrum analysis technology as the research background,overlapping rate and 100% POI are important for system to capture and analyze mutation signal.Faced with large bandwidth,high speed real-time processing data in real time analysis of overlapping rate and 100% POI index,this paper proposes a kind of parallel frequency domain digital signal processing architecture design based on ADC + FPGA + DDR4 hardware platform.This parallel frequency-domain digital signal processing architecture uses delay control to allocate IQ baseband data into parallel multiplexing according to overlapping rate,and then adopts parallel variable overlapping rate architecture to design corresponding overlaps.After overlapped processing,the actual data rate of IQ baseband data is multiplied,far exceeding the high-speed clock frequency of the system.Therefore,the subsequent FFT calculation and detection processing adopt parallel architecture to reduce the difficulties of high-speed data processing.Finally,the final detection result is obtained after further processing the detection output according to the detection mode.The variable overlap of parallel architecture is mainly designed to control the readwrite process of dual-port RAM,which is realized by the way of address read-back.The address read-back is determined by the overlapping rate and the number of parallel paths.In parallel architecture,FFT computing process includes positive data synchronization control,FFT calculation,amplitude calculation,logarithm calculation and output order adjustment.In detection module,three types of detection modes,e.g.,positive peak,negative peak and averaging,are designed.There are several parts including parallel architecture positive data synchronization control,detection processing based on switch structure,detection mode control and parallel detection output result merging.The design,simulation and implementation of the whole system in this project utilise Vivado,MATLAB,modelsim and other software,signal source,spectrum analyzer,oscilloscope and other instruments to debug the system through.