Research And Implementation On Integrated Baseband Algorithms For Telemetry And Telecontrol Receivers

For various ground station equipments and aerospace telemetry and telecontrol terminals,such as launch vehicle telemetry and telecontrol,deep space telemetry and telecontrol,and relay satellite telemetry and telecontrol,the traditional solution is to design a set of telemetry and telecontrol equipment for each signal system,in order to meet the requirements of the tasks.The setting of the parameters should be completed at the beginning,including modulation type,carrier frequency,symbol rate,coding mode,and frame structure,and develop corresponding functional modules.If a variety of task types is compatible at the same time,it will result in a larger device,large number of functional modules,and less generalization.Therefore,it is of great significance to study the integrated baseband receivers,which adapts to multiple tasks at the same time,for telemetering and controlling.The dissertation focuses on the baseband system of the telemetry and telecontrol receivers,which needs the integrated baseband requirements of the multi-task ground monitoring station and the detection station.The details are as follows:(1)The baseband scheme of the telemetry and telecontrol receivers is designed,which supports both the spread spectrum and non-spread spectrum modes.The algorithms are designed,including Pseudo-noise code synchronization,carrier synchronization,bit synchronization and frame synchronization algorithms.The solution has many advantages,such as miniaturization of hardware platform and integration of baseband algorithms.(2)Aiming at the optimal threshold setting problem in the pseudo-code capture phase,an adaptive threshold algorithm based on the SNR is designed to improve the detection probability,integrating the fixed threshold and the adaptive threshold algorithm.(3)For the long code capture problem of the telemetry and telecontrol system,a multi-path parallel long code acquisition algorithm is proposed,in order to achieve fast capture of long codes under short code guidance conditions.The analysis shows that the average acquisition time of the four-way parallel capture scheme is shorter than before the improvement,and the acquisition speed is greatly improved with less hardware resources.(4)The schemes of download carrier synchronization in the spread spectrum and non-spread spectrum mode are designed.In the spread spectrum mode,the time-frequency two-dimensional search algorithm completes the PNcode capture and reduce the frequency error.Then,the frequency-locked loop is started to complete the compensation of the residual frequency difference,and finally the carrier phase tracking is completed by the phase-locked loop.In the non-spreading mode,the FFT algorithm is used to complete the carrier frequency offset acquisition,and the COSTAS loop is turned on to track the carrier phase,after the carrier frequency offset is pulled to a small error range.At the same time,the characteristics of the phase-detection algorithms in the two modes are compared,where the simulation results show that the inverse tangent algorithm with more hardware resource consumption converges faster than the hard-decision phase-detection algorithm.(5)The bit timing synchronization algorithm is designed according to Gardner algorithm,where the timing error detection,interpolation filter and interpolation controller are designed in detail.The Gardner algorithm is employed to complete timing error detection,and segmented parabola is adopted to implement interpolation filter,and the simulation results show that the method can complete the bit synchronization of multi-rate signals.At the same time,the frame synchronization algorithm is designed which adapts to different coding methods and signal patterns.(6)This Verilog HDL language are used for hardware programming implementation and functional verification on the FPGA platform,and total test of the key algorithm modules are performed.The test results show that all the indicators meet the requirements,which consumes Intel Stratix IV EP4SE8206 FPGA 68% of the hardware logic resources.