Design And Implementation Of AIS Baseband Hardware Platform And Slot Synchronization

With the continuous development of economic globalization, the shipping traffic at sea develops rapidly. A significant increase in the number of ships at sea makes the probability of ship collision increase greatly. Automatic Identification System (AIS) enables ship to ship, ship to shore and shore to ship communications in a real-time and accurate way, as a result, the safety of navigation can be protected, and the management of the offshore ships can be performed effectively, so it is widely used.AIS equipment is normally composed of the embedded microprocessor, AIS dedicated baseband signal processing chip, radio front end and human-machine interfaces. This thesis uses FPGA as data processing and control unit to construct an AIS baseband signal processing hardware platform based on the software radio concept. The main work can be divided into three parts. The first part is the design and implementation of FPGA-based AIS baseband hardware, the second part is the AIS baseband hardware driver program design, and the third part is the software design of the AIS time slot synchronization.This thesis firstly studies the AIS system performance criteria, technical characteristics, development trends, and analyses the hierarchical structure of the AIS communication protocol, AIS system components and the function of each part. Secondly, based on the existing AIS hardware design research, the FPGA-based AIS baseband signal processing hardware platform is designed and implemented, and each function module of the platform is specifically introduced, including the control module, GMSK modulation and demodulation module, FSK modulation and demodulation module, external memory unit module, serial communication interface module and USB communication interface module. Consequently, the underlying driver programs which can be used to test the function of each designed module are designed, and the AIS time slot synchronization program is designed to achieve the function of synchronizion with the UTC directly. Finally, the test results of each functional module and the time slot synchronization are given, and the test results are analyzed.