| In order to alleviate traffic congestion,more and more cities now use Electronic Toll Collection(ETC)at toll stations.This paper is based on 5.8GHz ETC application to analyze and design the fractional-N frequency divider of PLL.In wireless communication systems,such as ETC,frequency synthesizer plays a unique role.It is the core module of radio frequency chip in a wireless transceiver.It can provide a stable,high precision,programmable and low noise local oscillator signal for the whole circuit.Sigma-delta fractional-N frequency synthesizer has attracted a lot of attention because of its low phase noise,minimum frequency step size not limit to integer times of reference frequency,high resolution and fast switching speed.And these advantages are mainly due to fractional-N frequency divider.Because it is the bridge of the whole frequency synthesizer from high frequency to low frequency,where the high frequency signal output by VCO changes into a low frequency signal passing through the fractional divider.The signal is used as an input of the phase frequency detector.It is compared to the reference frequency.At the same time,the fractional-N divider is also the key and prerequisite for the whole circuit to work in high frequency environment with low power consumption.So it is very necessary to research and design a high quality fractional divider.However,with the in-depth study of fractional divider,researchers found that it is not perfect with,spur as its non-negligible shortcomings.Because spur is very close to the center frequency,it is very difficult to filter out through a filter.Therefore,the suppression of fractional spurious is an important work in the design of fractional-N frequency divider.The specific arrangement of this thesis is as follows:1.Fractional-to-frequency ratio implementation: The output of sigma delta modulator is a control signal that controls the instantaneous division ratio of the multimode divider.It then it averages over a certain period of time;2.Improved 2/3 frequency divider: An improved 3-input TSPC latch is proposed based on the traditional 9-transistor 2-input TSPC through circuit analysis.On this basis,a 2/3 pre-divider with different structure is proposed.3.The suppression of fractional spurious: sigma delta modulator is the main method to suppress fractional spurious because of its stability,noise shaping and low power consumption.In this paper,the structure of sigma delta modulator is modeled and simulated by Simulink.An improved method to suppress fractional spurious is proposed,which combines random jitter and SDM.The structure order of sigma delta modulator and the influence of input data are compared and analyzed.4.Design of fractional frequency divider for 5.8G ETC system: This work designs a fractional divider for 5.8G ETC chip based on SMIC 0.13 um process.The frequency division range is 64~127,and the minimum frequency step is: 500 Hz,the layout area is 19.187um2,and the power consumption is 0.26 mA when the VDD voltage is 1.5V.The flow test results show that the fractional divider can accurately realize the fractional division ratio required by the system,and it can effectively suppress fractional spurs.Finally,the design flow of the fractional-N divider in the 5.8G ETC chip is summarized in detail. |
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