Design And Implementation Of High Speed Clock Data Recovery Circuit Based On BCD350 Process

Clock data recovery is the most critical technology in the design of high-speed serial transceiver.Generally,in serial communication,the sender does not provide the receiver with a clock synchronized with the serial data,which is asynchronous to the receiver.Because the data signal also has large attenuation after transmission channels such as cable,backplane and chip IO,and the transmission channel also has parasitic characteristics,the data after transmission will contain a lot of noise components,and the amplitude and phase of the data waveform will be offset.Therefore,the receiver needs to recover a clock from the data that can sample the data correctly.The clock data recovery circuit described in this paper uses Huahong BCD350 nm technology to realize a data clock recovery circuit with a static clock deviation of less than 100 ps,which is used to provide a clock for the internal sampling circuit of a high-speed signal receiving chip.By judging the phase relationship between the current output clock and data and adjusting the clock phase,the clock data recovery circuit is suitable for data sampling.The phase relationship between the recovered clock and data determines the bit error rate of data sampling results.Because the CDR loop uses a Hogge phase discriminator,the locking range is small,it is difficult to re-lock the loop when it loses lock,and it is possible to mistakenly lock the loop in the harmonic frequency of several times of the input data bit rate during the capture process after losing lock.The clock data recovery loop contains two loops,PLL and CDR,which can switch each other,to speed up the capture of the loop.Cheng,these two loops share modules such as CP and VCO.Therefore,they are all third-order loops with CPs.The common second-order passive RC is used as loop filter.First,the loop is switched to PLL loop.The frequency discriminator uses the input reference clock as the benchmark to quickly lock the clock generated by the loop.Then the loop is switched to CDR loop.The Hogge phase discriminator module locks the loop phase according to the input serial data and adjusts the clock phase to the maximum.Suitable for data sampling location.Based on some non-ideal characteristics of BCD350 nm process,several modules are designed and implemented independently to ensure the normal operation of the circuit after streaming: NPN transistor is used as the first stage op-amp in the receiving op-amp circuit,and a part of RC structure is added to equalize the received low-quality signal,and power jitter suppression module is added to the oscillator to reduce clock jitter.In order to improve the reliability of the chip in the actual working environment,this paper also adds reference voltage and current source,frequency detection circuit and other peripheral auxiliary modules to the clock data recovery loop.The simulation results show that the clock data recovery circuit designed in this paper uses Huahong BCD350 nm technology,and can support the data with a maximum rate of 333 Mbps at each limit process angle.The circuit can work normally at temperatures ranging from-55 to 125 C.The maximum operating frequency clock static offset is 56.29 ps,the maximum operating current is 27.44 m A,and the maximum power consumption is 150.92 m W.The performance of the clock data recovery circuit designed in this paper is in line with the design specifications,and the overall performance of the high-speed signal receiver chip is also in line with expectations.