Hardened Design Of SET In High-speed Phase Interpolation Clock And Data Recovery Circuit

With the rapid development of the aerospace industry in our country,the electronic equipment in satellite is asked for heavier tasks and the aerospace system demand higher data transmission rates than before.Mostly used as a electronic and parts of the logic sub layer in physical layer of high speed transmission protocol,the high speed serial data transmission circuit(SerDes)is widely used in aerospace equipment,so it is necessary to study the sensitivity of SerDes circuit which works in the radiation environment.And the radiation-hardened study of the Clock and Data Recovery Circuit(CDR)which is uesd as the core module in the SerDes circuit is also the important part of the SerDes system.The recent studies have showed that the circuits which are designed by nanometer leve technology become more sensitive for Single-Event Effect(SEE)with the reduction of the process dimension.Which is a typical digital-analog mixed circuit,the CDR is seldom discussed under the SEE in recent research.For example,we don’t know how well it will work under the action of Single-Event Transient(SET),and how to use the Radiation-Harden-By-Design(RHBD)to deduce the interference of SET occur in the CDR,and we can’t solve these problems refer to recent research findings,so we will talk about these two aspects in this dissertation. we have studied a high-speed phase interpolation CDR,and the research mainly includes the following aspects:Firstly,we will study how the CDR circuit work.From the circuit level and system level analysis we can find circuit sensitive nodes.As the CDR in our study is a digital-analog mixed circuit,and the analysis method of these two kinds of circuits is different in SET test,we will use different detection method for each parts respectively.As a result,we find that the most sensitive parts of in the digital part of the CDR are the Accumulator(saturating Accumulator and cycle accumulator)And in the analog part of the CDR are the high speed Sampler.And then,we will use the RHBD to deduce the interference of SET occur in the CDR.In this dissertation,we will introduce a self-error-detected and self-error-corrected circuit to detect and correct the error in the FSM;As for the high speed Sampler,we will hanrden the circuit by adding shorted PMOS in circuit level and introduce a special layout design.As a result we rise the sensitivity threshold of particular MOSFET.Finally,we will aim at the layout design of the modified part of the circuit,and simulate the circuit after layout design to ensure whether this circuit can work well after modification.For each part of the layout,the area of the FSM is only increased by 10%,the area of the Sampler is increased by 15%.But as a whole,the area of the CDR is similar to the original,while the error endurance can be greatly increased at the same time.