Design Of FPGA For Aircraft Target Detection In High Resolution SAR Images

Synthetic Aperture Radar(SAR)is widely used in military investigation,surface survey and other fields because of its all-weather,all-weather and strong penetrating capability.For high-resolution SAR images,because of its high resolution,it not only brings us rich information,but increases the processor burden,and increases the running time of the algorithm.In order to speed up the convergence of the algorithm,it is necessary for us to use the embedded equipment to accelerate and optimize the algorithm.The FPGA(Field-Programmable Gate Array)has a large number of logical resources,with strong parallel capability,low power consumption,low latency and reprogrammable features,So it has a unique advantage in the acceleration of the algorithm.Open CL(Open Computing Language)is a cross-platform parallel computing framework.using the Open CL language to develop the FPGA has a shorter development cycle than Verilog and other hardware description language(HDL).For most software developers who are not proficient in the hardware resources of FPGA,it is very convenient to use Open CL language to develop FPGA.This paper mainly describes the optimization and acceleration process of the high-resolution SAR image plane target detection algorithm on the heterogeneous platform,and compares the running time and the detection effect of the algorithm on the CPU and the heterogeneous platform.The following work has been done around this theme.(1)The parallel structure of aircraft target detection algorithm in high-resolution SAR image is designed and implemented on FPGA.The algorithms that need to be implemented in parallel include airport runway detection algorithm,runway orientation algorithm,bright line detection algorithm,stop position template matching algorithm and aircraft template matching algorithm.This development uses C++ language to carry on the host program design,uses the Open CL language to carry on the kernel program design.In implementing these algorithms,we try to import image data into the local cache of Open CL,and when allocating workgroups,we need to be aware that the access complexity of work items within each workgroup to global memory cannot be too high.By this way,we can significantly reduce memory access time.(2)The parallel algorithm is further optimized by using the performance optimization method of FPGA.The optimization strategies include memory access optimization,vectorization,loop expansion and pipeline replication.Some optimization work has been done in programming,such as using bit operation instead of multiplication and division operation,using bit operation instead of data exchange operation,using built-in function of Open CL instead of library function of C language,etc.In this paper,we compared the detection rate,false alarm rate and algorithm convergence time between CPU platform and heterogeneous platform.As you can see,the running time of the algorithm on heterogeneous platforms is much shorter than that of CPU.However,while we pursue the convergence speed of the algorithm,we properly lose the performance of the algorithm.As a result,the detection rate has been slightly reduced.