Design And Verification Of Digital Part Of Programmable Power Management Chip

With the increasing variety of embedded devices and application scenarios,the power management requirements of embedded system have become increasingly stringent.PM26 is a programable system-level power management IC,which can flexibly deploy various power management strategies,monitor the power status in real time,shorten the delay of control loop,and implement the power management functions for embedded system in various complex application scenarios by running the power management program on the chip.According to the architecture and digital/analog circuit division of PM26,this thesis designs and implements the digital part of PM26.The main work of this thesis is as follows:1.This thesis has designed the composition structure,module division and working principle of PM26’s digital part,defined the functions of each module,and formulated the module design and integration route of PM26’s digital parts are.2.This thesis has completed the RTL design of the main modules of PM26’s digital part,such as the Buck switch-power controller,I3 C communication interface,clock/reset module,and fault/interrupt controller,and integrated these modules through the unified register interface and register address allocation to form the complete digital part of PM26.After the completion of system integration,the thesis has designed the system power-on/power-off controller at the top level of the digital part,which is the main state machine of the power management system and the bridge between software and hardware.3.This thesis has established the verification plan for PM26’s digital part,determined the function points to be covered in the verification,built a verification platform to carry out the function simulation of each digital module and system verification of the while digital part,and designed test cases supporting randomized excitation to carry out regression test to complete coverage analysis and verify convergence.At present,PM26 has realized chip flow and delivery,continued to track defects and faults after chip delivery,and completed product optimization and iteration.