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Research On Parallel ECT Data Acquisition System Based On FPGA

Posted on:2021-05-02Degree:MasterType:Thesis
Country:ChinaCandidate:S L CuiFull Text:PDF
GTID:2392330611468775Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
Traditional electrical capacitance tomography(Electrical Capacitance Tomography,ECT)system serial measurement mode is difficult to capture the transient state information of exhaust gas at the aeroengine tail nozzle High-speed parallel ECT data acquisition system,with 5 field programmable gate array(FPGA)chips as the core control,to achieve the purpose of improving the data acquisition part of the throughput,and thus improve the system response speed,for monitoring the exhaust of the aero engine tail nozzle It is very important.This paper deeply studies and solves the problems of multi-core controller coordination,multi-channel data synchronous acquisition,phase-sensitive demodulation and transmission in the design of parallel mode electrical capacitance tomography system.The main work and results are as follows:1.A parallel ECT data acquisition system based on 5 FPGAs is designed.The system is divided into two levels.The first level is data acquisition and digital phase sensitive demodulation algorithm processing.The second level is responsible for the communication between the FPGA system and the PC host computer..Take advantage of the parallel processing of FPGA to reduce the time spent in the circular calculation queue in the processor,and divide the entire system into an incentive source main controller,coprocessor,communication module,and perform system-level fusion debugging according to the function realization.Effectively improve the overall data throughput rate of the system.2.The first stage of the system includes C / V conversion,anti-aliasing filtering,analog-to-digital conversion,and three coprocessors for digital phase-sensitive demodulation.The data transmission between the two stages uses multi-channel cascade SPI communication.Summarize the coprocessor data to the second-level FPGA + USB3.0 communication end,and another independent FPGA chip is responsible for solving multiple digital phases between 3 FPGAs by using level jump trigger and synchronous phase-locked signal.The synchronization problem of the sensitive demodulation channel makes the single-cycle demodulation points of each channel data consistent,improves the demodulation accuracy,and ensures the orderly transmission of the data of each channel to the upper computer.3.The second level of the system is FPGA,which is responsible for data screening and communication interface of PC host computer.The communication module adopts USB3.0 high-speed communication board,which effectively improves the system data transmission capacity.The analysis of digital signal transmission is based on the principle of digital phase-sensitive demodulation,appropriately increasing the multiply-accumulate period,seeking to maximize the co-correlation between the input signal and the reference signal,reducing the demodulation error,and improving the accuracy of the data acquisition operation.4.Completed the static performance test of the system,combined with the delay time of each module circuit of the system,and made a theoretical calculation and evaluation of the dynamic performance of the system,that is,the imaging rate was 900 frames,which reached the minimum frame rate for monitoring the exhaust of the aeroengine and optimized the design of the parallel ECT system Some suggestions were made.
Keywords/Search Tags:Electrical Capacitance Tomography, Digital Phase Sensitive, Demodulation, Field Programmable Gate Arrays, Data communication
PDF Full Text Request
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