Application Research Of FPGA In Railway Signal Cable Fault Detection

The importance of railway signal cable to the railway system cannot be ignored.The type and frequency of railway signal cable fault increase,which makes the cable fault detection more difficult.At present,the domestic cable fault detection research is still in the initial stage of development.It is of considerable significance to study a set of fault detectors with high accuracy,less error,and easy operation for the safety of train operation.Due to the large-scale laying of railway lines,the current troubleshooting generally needs more workforce and time.Therefore,the purpose of this thesis is to realize the detection of railway signal cable fault based on FPGA by using chaotic test sequence,and to complete the fault location and fault type feedback.The main content of this thesis is to use FPGA resources to design the detection end of the chaos test signal generator and signal acquisition module,as well as the terminal to output the final results.This thesis uses FPGA resources to generate Logistic chaotic sequence,analyzes and determines mapping parameters,and then uses its DDS function to design test signals generator.After digital modulation,the task of digital to analog conversion of test signals is realized by DAC.FPGA provides the driver of test signal generator module,which can control the frequency of test signals.The acquisition module uses the ADC chip with high-frequency sampling rate,which is driven by FPGA to convert the mixed analog signals in the cable into digital signals.First,preprocess the acquisition data,then upload the acquisition data to the terminal equipment,and then save the data,calculate the fault distance,and judge the type at the terminal.This thesis introduces the basic principles,research framework,key technologies,and key breakthroughs of the design.The hardware and software algorithm design of the main control module,DAC,ADC,serial port,and other modules of the detection end are completed,and the simulation,hardware debugging,and actual test are carried out in the laboratory.The results show that the scheme proposed in this thesis makes the error smaller,and the measurement distance longer than traditional SSTDR method.There are 77 pictures,7 tables and 53 references.