| With the rapid development of smart terminal technolog y,various types of portable devices are more abundant in functions,and at the same time,the power consumption is increased rapidly and the battery life is not good.How to improve the charging speed is a new problem for people to solve the endurance of mobile intelligent terminals.The USB Power Delivery(USB PD)protocol specification introduced by USB-IF is an open fast charging standard that complements the Type-C interface and has the potential to unify interface specifications in the fast charging field.Therefore,the research on the USB PD fast charging standard is of great significance.This thesis elaborates on the architecture of USB PD3.0 protocol,the communication mechanism and packet format based on the original message sequence,and the control principle of constant voltage mode and continuous mode of QC3.0 protocol.A Source-port dual-port fast charge control system compatible with USB PD3.0 protocol is designed.The USB Type-C port is compatible with USB PD3.0 and QC3.0 protocols,and the USB Type-A port supports QC3.0 protocol.Design of device policy management layer,policy engine layer,protocol layer and physical layer in dual port manager and USB PD3.0 protocol and design of low voltage controller and high voltage controller in QC3.0 protocol using Verilog-2005 hardware description language.The drive authority assignment to the AC-DC power supply is accomplished through the design of the dual port manager.At the device policy engine layer,the management of the AC-DC power supply and the control of the Type-C interface are completed through the design of the power configuration,the power supply negotiation,the power supply,and the power hard reset module.At the policy engine layer,the design of the finite state machine is used to complete the communication control based on the original message sequence..At the protocol layer,through the design of the transmitter module,the message is sent and the Rp resistance is controlled.The receiver module is designed to implement the message parsing.The design of the hard reset controller module ensures the security and stability of the system.The physical layer transmission path is calculated by using CRC-32 and 4B/5B coding.And the BMC coding completes the transmission protection of t he data packet,the acceptance path uses BMC decoding,4B/5B decoding,and CRC-32 verification to complete the stable reception of the data packet.Through the design of the low-voltage controller,the control of the dual-port cooperative operation is comp leted,and the design of the high-voltage controller realizes the switching between the constant voltage mode and the continuous mode.The proposed FIR filter based BMC decoding scheme achieves a significant improvement in decoding stability compared to the conventional oversampling method.The design of the design is verified by VCS simulation tool.The simulation results show that the design meets the protocol specification and realizes the Fix power mode and PPS power supply mode of USB PD3.0 protocol,a nd supports the power output of 1-7 power levels,the highest output power is 100W;In addition,the QC3.0 protocol's constant voltage mode 5V/3A,9V/2A,12V/1.5V and continuous mode 3.3V-12V/3A power supply output,the maximum output power is 36W;The 5V/ 5A power supply output when the port is working at the same time,the output power is 25 W.Compared with the traditional power control system,this design greatly improves the charging power,and the compatibility is significantly improved.Finally,the physical design is realized by Huali 0.35 um 1P3M process.The USB interface peripheral circuit is equipped with the Power-Z protocol analyzer for discharge test through the FPGA development board.The test results show that the discharge power is 0-33 W dynamic output,achieving the expected goal of high power fast charge. |
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