Design And Implement Of Self-Repair Module In SRAM Chip

As the size of the chip manufacturing process decreases,the probability of the failure is greater because the high density of memory,this leads the reduction of manufacturing yield and the increase of chip manufacturing cost.To solve the problem of manufacturing low yield,the improved fabrication methods can be used.On the other hand,the self-repair function can be added into the chip from the beginning of the chip design,and finally to promote the yield of the memory manufacturing.There are three kinds of memory self-repair schemes involved in this paper:RM(repair most)、ESP(essential spare pivoting)、RR(random repair).In the paper,the three schemes are introduced and analyzed with practical examples in detail.Each of the three schemes has specific emphasis,and there are great differences in the treatment of the fault address.Finally,the three aspects of the area ratio,repair rate and test time were compared and the cost was evaluated in this paper.The Self-repair SRAM chips designed in the paper passes the main chip design flow of pre-and post-simulation,design compile,timing analysis,and the post-routing,the final physical layout was obtained.The actual chip design flow can provide two analysis parameters of area ratio and test time.The repair rate parameters need to be combined with the previous test data,and the Monte Carlo analysis method is used.After the self-repair scheme is adopted,if the repair rate is taken to evaluate the number of additional qualified memory,the results shown that RM has the same effect as ESP,and RR is the lowest.If the area ratio is used to assess additional chip area needed,the analysis results shown that RR occupies the largest proportion,RM is next,ESP is the minimum.If the test time is employed to examine the chip test cost,the results shown that the RM scheme is the highest,ESP is next,and RR is the lowest.Among them,repair rate brings benefits,the area ratio and the test time produce additional expenses,and the difference between them is the final cost-benefit.The results of cost-benefit analysis show that the three self-repair schemes can bring cost benefits,the ESP scheme has the highest income of 14.9%,RM is followed of 12.5%,and the RR is the lowest of 6.2%.Through the analysis of the above three parameters,the ESP self-repair scheme has the strongest applicability to the memory,which can bring the maximum cost benefit and reduce the cost of the chip manufacturing.