Design And Simulation Of SWP Interface Applied To Mobile Payment

Mobile payment is a method that a user makes payment of the product he buys or the service he gets by his mobile terminal equipment(usually stands for mobile phone).NFC payment is a technique that works between near field communication terminal and financial internet device to achieve the function of data interaction and payment.NFC is a kind of short distance contactless technique.It works in13.56 MHz frequency band within 10 CM of transmission distance.Compared with other wireless communication technique such as infrared communication and Bluetooth,NFC has huge advantages of power dissipation,efficiency and particularly important security,so NFC got a lot of attention in the area of mobile payment.NFC has several implementation scheme.The mainstream scheme is SWP-SIM plan at home and abroad.Single Wire Protocol(SWP)makes rules of the way of connecting and communication standard between CLF contactless front end chip and SIM card.This paper introduces the protocol which is TS102613 communication protocol firstly that the SWP interface is based on.It introduces each function detail and communication standard in Physical transport layer and Data link layer.With the full understanding of the protocol,it comes up with the overall structure and designing scheme of SWP interface and explains every detail about the process of the designing of SWP interface,including: functional performance of SWP interface,overall structure and brief descriptions of each function module,function details and logic of RTL code by Hardware Description Language Verilog of each function module.In order to reduce the power consumption of the system,finite state machine and coding style of clock gating are involved in the designing and coding process.The state is transferred according to the two states set in advance by the controlling signal,and the unnecessary power consumption is reduced by the dynamic switching state.Clock gating is a time pulse signal technology in the synchronous sequential logic circuit which reduces the power consumption of the chip by turning off the clock that is temporarily unavailable.Later,it is the platform simulation of RTL code.It includes building testing platform,writing testing files,running RTL code,loading testing vectors,gaining testing results,analyzing the outcome and over and over modification until it can actually works.Finally,summarize the whole paper and come up with the further working direction.