Design And Realization Of JPEG Hardware Decoder Based On FPGA

In the 21st century,mankind goes into the information age, as the main carrier of information dissemination, the image plays an important role in social development. With good compression performance, JPEG still image compression standard has been widely applied in the image field. At the same time, with the maturity of integrated circuit technology, it has become a hot spot that FPGA hardware is used to realize image processing algorithm, so using hardware to process image has practical value.Research work focuses on the hardware design and realization of JPEG baseline system decoder, and the order is to provide a source code to support the JPEG decoder. On the basis of a brief introduction of JPEG coding and decoding theory and JFIF format commonly used, the hardware structure of the decoder is proposed on the general prospect. The top-down and modular approach are used in the design, and verilog hardware language is used to describe the decoder. Each module is independent and can be reused. The mainwork of the paper includes the following aspects:1. The coding and decoding principle of JPEG Baseline System was studied in depth. After analyzing and comparing the exist algorithms which were included by the system, the best optimal algorithm suitable for hardware implementation was chosen. And then the overall hardware design of decoder was put forward;2. Based on the proposed scheme, verilog hardware language was used to describe and RTL function simulation was done for each module with modelsim simulation tools, the simulation results were compared with the theoretical value. RTL joint debugging was achieved on the basis of each module's correct functional simulation, and the FPGA prototype validity was finished on the chip EP2C35 of CycloneII series produced by Altera Company. The simulation and verification results show that the decoder meets the expected requirements essentially, and achieves a higher operating frequency in the premise of ensuring undistorted images;3. According to the characteristics of FPGA realizing, the decoding algorithm is optimized. In the entropy decoding stage, entropy decoding algorithm was improved combined with the construction of the Huffman tree, so the decoding time does not change with the size of code length. In the IDCT operation stage, the decoding speed was speeded up and the number of multipliers was reduced by pipeline technology.Developing integrated circuit core nuclear of intelligent property is the current trend .By designing and realizing hardware structure of JPEG Baseline System, the development of integrated circuit technology in our country is promoted, and also it has a positive significance in hardware designing of other image decoding systems.