Design Of A High Speed Sram Circuit In The Substation-box Which Is Oriented Towards The Reconfigurable Block Cipher Algorithm

Substitution box is the only nonlinear module in the symmetric key algorithms.It is the key point of the security of the password.Over 70%of block cipher algorithms use this structure.Substitution box is the most important part of the whole block cipher algorithm,it has a high concurrent access.In traditional design,substitution box account for 30%-50%area of the entire algorithm.Multi ports memory can effectively settle the demand of the high concurrent access of substitution box.A memory with high area efficiency has great significance to the area afficiency increasing of algorithms.The main work of this paper includes:(1)summarize the commonly used multi-port memory circuits,find out their respective advantages and disadvantages and the scope of application.(2)A multi ports SRAM bitcell design based on the sharing of pull down transistor scheme is proposed.The bitcell has four read ports and a write port.The area efficiency is improved through the sharing of pull down transistor and overlap of multiple metal layers.The speed of read operation is increased by adjust of the size of pull down transistor.The stability of read operation is improved with the read decupled structure.(3)A new structure of dynamic decoding circuit based on multi-level dynamic decoding circuit.With the help of feedback circuit,the speed of decoding increases and the energy comsumption goes down.A 256 X 8 multi ports memory circuit with 4 read ports and 1 write port is completed in SMIC 40nm process.The total area of this circuit is 6020um2,and normalized to 1505um2.Compared with the memory circuit generated by memory compiler,the efficiency of area increases by 27%.The post-layout simulation results indicate that the delay of this memory design is 0.795ns at 1.1V.It has a 25%reduction of time compared with the single-port memory genrated by memory compiler.