Implementation Of High-Precision And Wide-Range Time-to-Digital Converter

Accurate time interval measurement technology has been widely used in scientific research,engineering practice,military aviation and so on.Time to Digital Converter(TDC)is used as a dedicated time interval measurement circuit for converting continuous time interval defined by two asynchronous signal into digital signal and gained rapid development with the wide application of time interval measurement technology.In the application of temperature sensing detection,TDC as a special analog to digital converter(ADC),is used to replace the traditional ADC,solving the problem that the degradation of ADC's performance under the advanced CMOS technology restraicts the improvement of temperature sensor.According to the design requirements of high accuracy,wide range and high stability in temperature sensing detection,this paper presents a three-stage TDC based on the sliding scale method.Firstly,in order to reduce nonlinear,improve the quantization accuracy of TDC,the sliding scale method is adopted in the designing of the three-stage TDC by further quantifing the initial and final phases respectively.In this paper,the three-level TDC adopts multi-stage conversion scheme.realizing the measurement range and resolution at the same time.Besides,the quantization resolution of high,middle and low-level TDC is generated by closed-loop feedback control circuit in order to improve the stability of the system.The closed-loop feedback control circuit delay-locked loop(DLL)is adopted to generate accurate periodic clock signal and a uniform clock multi-phase,where the precise clock cycle used as the resolution of high-level TDC,cooperates with a counter forming the high-level counting TDC for expanding the meaurement range.The uniform clock multi-phase as the resolution of middle-level TDC is used to quantify the quantization error of the high-level TDC.Finally,based on the the principle of the parallel scaled delay line TDC,the modified sub-gate delay line TDC structure is proposed to realize the sub-gate delay time resolution,which is generated by the closed-loop feedback control circuit.Compared with the published two-stage TDC structure,the three-level TDC proposed in this paper not only takes the measurement range and resolution into account,but also improves the precision and stability of the system by using sliding scale method and closed-loop feedback control logic,obviously meets the demand of temperature sensing detection.Fabricated in GSMC 0.18μm CMOS technology,the Cadence EDA tools is adopted to complete the entire circuit's pre-simulation,layout,post-simulation.The TDC project achieved tape-out with two other design program together for MPW wafer verification,the total circuit area is 1951.91μm × 992.88μm,which TDC occupies the area of 877.51μm × 992.88μm.Measurement results show that:under the conditions of 125MHz input reference clock,1.8V supply voltage and room temperature 27℃,this three-level TDC achieves 4.08μs measurement range and 250ps resolution.The DNL is within-0.26LSB-0.30LSB,INL is within-0.42LSB-0.46LSB,and Single-Shot Precision(SSP)is 0.91LSB.In addition,the measured results from-20℃ to 100℃ are all meet the design requirements.