Design Of Delay Locked Loop In High Precision Pipeline ADC

Pipeline ADC(Analog to Digital Converter,ADC)is widely used in precision instruments,communication base stations and various electronic devices.In recent years,the complexity and integration of pipeline ADCs have increased exponentially,and traditional clock schemes have been unable to meet the high-speed and high-precision requirements of ADCs.Accordingly,this paper designs a Delay Locked Loop(Delay Locked Loop,DLL)circuit applied to a high-precision pipeline ADC,which can provide a low-jitter,multi-phase and high-precision clock.This paper analyzes and designs the key modules and auxiliary modules in the delay locked loop,adopts the top-down idea,and determines the performance index of the delay locked loop from the clock index requirements of the ADC;further selects the top-level circuit structure,Analyze the constraints between key modules and determine key design parameters;then go deep into each module to analyze specific circuit designs,including device selection,non-ideal factors,and performance optimization.In terms of loop parameter design,this paper deduces the transfer function of the overall loop and sub-modules in detail,and on this basis,calculates parameters such as bandwidth.In terms of noise estimation,the noise parameter model of each sub-module is established.Based on this model,the phase noise of the entire loop is estimated at the early stage of design,and the circuit design is guided.In the aspect of circuit design,an anti-error lock control structure is proposed,which effectively solves the problems of dead lock or harmonic lock in the traditional DLL,and greatly improves the accuracy and speed of the DLL circuit;In order to adapt to the different operating frequencies of the delay phase-locked loop,the charge pump charge and discharge current and the voltage-controlled delay line delay range are set to be adjustable in registers.Based on the above circuit structure,a delay locked loop circuit with 100 clock outputs is designed and implemented.When the voltage is 1.8V,the static power consumption of the designed circuit is about6 m W.Driven by an ideal 20 MHz clock,the delay locked loop can be accurately locked within 2μs,the average output clock phase delay is 502 ps,the deterministic jitter is 2.12 ps,and the random jitter is 1.6ps.The post-simulation results show that it can meet the multi-sequence and highprecision requirements of circuits such as analog-to-digital converters.