Basic Research On Embedded Silicon Interposer Technology For Fan-Out Wafer Level Package

With the rapid development of the information society,people's demand for and dependence on smart devices continues to increase,both in appearance design and performance applications.The core of these smart devices is microelectronics chips that rely on semiconductor technology.The ITRS Semiconductor Technology Roadmap 2.0 report indicates that transistor size will no longer shrink after 2021,and chip-level integration and advanced packaging are considered to be the key path for continued breakthroughs in Moore's Law,and the fan-out wafer-level package is a typical representative of advanced packaging.According to the latest progress of fan-out wafer-level packaging technology at home and abroad,this paper proposes an embedded silicon interposer technology and designs two different types of embedded silicon interposers to realize a fan-out wafer level packaging stacking.The embedded interposer has several cavities,of which the sidewalls have metal wires crossing it,and the bottoms of the cavities have electrical interconnection structures vertically going through the substrate.Combining the wires and interconnection structures makes it electrical interconnections of both surface of substrate.The microelectronic chips are integrated at the bottom of the cavities by front-mounting or flip-chip bonding,and the electrical connection between the chips in different cavities can be achieved through the rewiring layer crossing the cavities of the top surface.By these means,a fan-out wafer-level 3D package is realized based on such embedded silicon interposers.The main research contents of this article are as follows:(1)For low-frequency digital IC fan-out wafer level packaging applications,a design of the embedded silicon interposer structure with low-resistance silicon pillars as electrical interconnection is proposed.A glass reflow process and a KOH wet etching process have been developed to achieve isolation of a low-resistance silicon pillar from a substrate on the bottom of cavity(Through Silicon Interposer,short for TSI).The influence of glass reflow temperature,aspect ratio and other factors on the filling depth of the glass reflow was studied.It was verified that the surface of the silicon interposer and the TSIs on the cavity were electrically connected through the metal wiring on the sidewall of the cavity,and the embedded silicon interposer was successfully prepared.At the same time,TSI resistance test and breakdown voltage test to evaluate its electrical properties.The TSI thermal stress distribution of the silicon interposer was tested using infrared photoelastic imaging technology,and also analyzed under the thermal cycle tests.The hermetical test was performed by using the helium mass spectrometry leak detection method(2)For the application of radio frequency microelectronics system-level packaging,a design of embedded silicon interposer based on hollow copper through silicon via(TSV)is proposed.Ultrasound-assisted TMAH wet etching silicon process is developed and a smooth surface on the cavity is realized with a surface roughness as low as 22.6 nm.A double-sided TSV electroplating process was developed to form a patterned metal layer on the two surfaces of the substrate,the surface of the substrate cavity and the sidewall of TSV hole.Samples of hollow copper TSV embedded silicon interposer were fabricated.(3)In order to verify the development of the embedded silicon interposer for RF microelectronics chip system packaging applications,a 3D stacked RF package structure and assembly process were designed,and the distribution of the thermal stress and thermoplastic strain generated during the integrated assembly process was simulated and analyzed.The influence of CPW transmission line density and TSV layout on its thermal stress was analyzed by simulation.The assembly and testing of RF chips are completed and verified feasibly.