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Research On Heteogeneous Multi-Core System Verification Technology Based On UVM

Posted on:2019-08-18Degree:MasterType:Thesis
Country:ChinaCandidate:Y S ShiFull Text:PDF
GTID:2428330548986775Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The heterogeneous multi-core system based on NOC(Network on Chip)utilizing the high bandwidth and high parallelism of NoC fully uses the parallel capability of the on-chip resources effectively and becomes the best solution for the high-density computing.As more and more functional clusters are introduced into multi-core systems through IP reuse technology,the scale and complexity of the system are increasing,and analysising and locating the defects and vulnerabilities in system become more and more difficult.Research on efficient verification technology based on multi-core systems has gradually become a hot topic in the industry.In this thesis,a system-level verification implementation method based on software simulation and verification framework based on UVM verification methodology are used.A verification environment for heterogeneous multi-core systems is designed and implemented,which realizes generation and driving of constrained random computing task configuration and data,automatic collection and check of computing output,coverage statistics and so on.The main work of the thesis is as follows:Firstly,the thesis makes a thorough analysis of related concepts of system-level verification,the frame structure of UVM and the structural characteristics of the target heterogeneous multi-core system.The overall requirements of verification are defined and the basic framework and communication mode of the verification environment are planned.Next,the thesis uses the "module" cycle accurate modeling strategy to design and implement the network function model;according to the details of the interaction between the verification environment and the Network Function Model,the Network-Interface Function Model is designed and implemented.The interface Universal verification component and the automatic check component are designed and implemented based on the UVM verification framework.The test suite is designed and implemented by the attributes of the computing task and the requirements of the test.Coverage statistic component is designed and implemented according to computing attributes contained in the computing task.Finally,the thesis evaluates function accuracy,validity and errors processing ability of verification environment by applying tasks of different constraints to the system.
Keywords/Search Tags:UVM, The heterogeneous multi-core system system, Functional verification, Software simulation
PDF Full Text Request
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