Logic Circuit Design For Test Based On SLTS Interface Of Chip

With the change of network clock synchronization technology,the internship company has proposed a new chip clock synchronization interface program-SLTS(Single Line Time Service)through technological optimization innovation.As a new chip interface,SLTS does not have a supporting chip test system,which makes it difficult to ensure the function of the SLTS interface after the chip is returned.In accordance with the needs of the company,the department where the internship is located is dedicated to the development of a chip automated test system for SLTS interface to complete the testing of the SLTS interface.The development of the chip automation test system includes hardware board level design,automation script design and SLTS test logic circuit design.This paper mainly designs and simulates the localbus module for register reading and writing,SLTS sending module and SLTS receiving module in the SLTS test logic circuit,and download it to the FPGA to analyze the measured results.The main research work includes:1)In order to solve the problem of MUC controling with test logic circuit,on the basis of an in-depth analysis of the localbus communication protocol,a register read/write module conforming to the localbus bus protocol was designed.The simulation results show that this module implements the register of the logic circuit in the MCU.Control,and thus to achieve the control of the entire test logic circuit.2)In order to solve the problem of 88 test vector generation and transmission,the state machine control method is used to generate and segment the test vector timing waveform segmentation,and a CRC arithmetic circuit sub-module is designed to realize the CRC in the test vector generation process.Real-time calculation of the check code,simulation results show that the module can complete the generation and transmission of 88 kinds of test cases.3)After the test vector is input to the tested chip,the pulse width of the response waveform of the tested chip needs to be detected and the data is presented.In this paper,the state machine is used to segment the response waveform.Each state is used to detect the pulse width,sample and store data,and a high-precision pulse width detection submodule is designed.Simulation results show that the module can correctly complete the data sampling of the response waveform.And pulse width detection,detection error of ± 5ns.4)Download the test logic to the FPGA and take A chip as an example.The test results show that the test system can give the expected test results in the case of normal clock synchronization and non-synchronization of the A chip.The test logic circuit designed in this paper meets the design requirements of the company.At present,the test system has been put into use.