Research On Key Technologies Of The Heterogeneous Multi-core SoC Platform SDK Supporting OpenCL

In the past,processor clock frequency has attracted most of processor vendors' attentions as a promising key indicator to evaluate performance of the processor.Thus,designing the processors with higher clock frequency becomes an active area of both industry and academic research.However,the increasing of single-core processor's frequency will encounter some issues including "frequency wall","power wall" and "memory wall".With the rapid development of integrated circuit technology,the processors turn to multi-core multi-threaded development.They are divided into homogeneous multi-core processors and heterogeneous multi-core processors.Heterogeneous multi-core architectures have been widely used in recent years benefited from the lower power consumption,lower cost and higher performance.The dissertation designs a heterogeneous multi-core System on Chip(SoC)platform.The platform uses a MicroBlaze soft-core processor as the host,and multiple OR1200 processor-based compute unit subsystems as the slave.The interconnection between the host and the compute unit is investigated.The host can access the memory of the compute unit through the AXI bus.Meanwhile,the host can read and write the reserved registers of the compute unit module through AXI-Lite interconnection model,thus realizing the control of the compute unit.The design of symmetrical dual-port block memory is introduced.The platform can flexibly switch between multiple symmetrical memories which is in the charged of the host.Hence,the host can more efficiently configure the memory of the compute unit.The compute unit can simultaneously fetch the instructions and the data from the memory.The compute unit can notify the host of the execution status of the task in an interrupt controller in real time.The dissertation investigates the heterogeneous multi-core system programming model.In addition,the designed platform can support the OpenCL standard.After analyzing the architecture of the platform,the dissertation focuses on the key points of the design and implementation of the compute unit subsystem.Firstly,analyze ORPSoC,memory organization,bootloader and testing.Then introduce the compute unit hardware and SDK design in this dissertation.In the hardware design part,the organization of memory has been optimized.The OR1200 adopts the Harvard architecture and combines with the Wishbone-to-SRAM memory access conversion module.The address modes for the memory access are unifiedly set to be Enable 32-bit Address.In the SDK design part,the compiler system is analyzed.The RAM memory is planned according to the design.The boot process is started,and the Makefile compilation script is designed.In order to verify the effectiveness of the proposed platform,we perform a simulation about compute unit subsystem.Finally,the heterogeneous multi-core SoC platform is verified on the Xilinx FPGA VC707 evaluation board.In order to demonstrate the feasibility of the platform,a memory test and a symmetric dual-port block memory switching test are performed.The test results show that the platform works well.Moreover,during the operation of the compute unit,the host can switch and configure another memory,which significantly improves the efficiency of the host configuration program.In addition,in the performance test,the complex calculation task is divided into multiple compute units and executed in parallel,which can effectively reduce the time for the execution of the calculation task.