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Study On The Design And Application Of Delay-based Physical Unclonable Function Based On The Parallel Scan Chain

Posted on:2018-02-05Degree:MasterType:Thesis
Country:ChinaCandidate:W X WangFull Text:PDF
GTID:2428330566998767Subject:Integrated circuit engineering
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Integrated circuits(ICs)have been widely applied in industry and people's daily life.Illegal copy and distribution of ICs are increasingly aggravated.This not only causes great economic loss to for the chip designer,but also the nation security is cast in a high risk when some sensitive chips are illegally distributed to the hackers.Effective countermeasures should be explored to protect the intellectual property(IP)of the chip designers.Physical Unclonable Function(PUF)has been widely investigated as a potent security primitive for ICs.To generate random digital signature,PUFs transform the intrinsic random variations in device parameters,such as threshold voltage Vth and channel length Leff,which arise from fundamental physical limitations in manufacturing process,to variations in circuit-level parameters(e.g.current and delay).Such transformation can typically construct a set of unique and random challenge-response pairs(CRPs)for a chip.A random key can be derived from a digital response from the PUF triggered by a digital input as challenge.Delay-based PUFs form a dominant class of silicon PUFs.They exploit the random variations in signal propagation delay due to variations in device parameters(e.g.Leff and Vth).Most existing delay-based PUF designs are independent of the original circuit.The extra PUF circuitry not only makes PUF vulnerable to removal attack,but also incurs high hardware overhead.In this work,the parallel scan design in original circuit design is exploited to implement PUF.The delay difference between one input signal passing two scan cells in two sub chains is used to generate PUF response.Two scan cells from two sub chains and an arbiter unit are combined to generate one PUF bit.The symmetrical SR-latch arbiter can determine which input arrives at the output of scan cell first.Compared to the scan-based PUF based on single scan chain,the proposed approach avoids the requirement of a rigorous clock of high frequency.It also reduces the area overhead due to PUF and improves the robustness against removal attack.The proposed PUF design is implemented on XILINX Virtex-5 FPGA boards.Experimental results show that its uniqueness is 49.86% and it also shows good randomness,and acceptable reliability under temperature and voltage variations.Scan-based side-channel attack has become a new threat to the cryptographic chips.Many countermeasures are proposed to safeguard scan design against the scan-based attacks.Among which,the methods based on lock and key scheme are more effective and popular.This scheme requires a safe golden key to authenticate the users of scan chain before testing.However,this poses great potential risk among the chips sharing the same golden key.How to keep the golden key confidential and how to assign each manufactured chip with a unique key are important issues to be solved.In this work,the proposed PUF design based on parallel scan design is adopted in the secure scan design to generate a unique key for each design.The uniqueness of PUF enables each chip taped out from one mask to hold a different golden key.Once the PUF is invoked for the first time,the PUF response will be hardcoded into the design so that even the environment changes,the PUF key information maintains.Also,only the chip designer can retrieve PUF key from a validation response under a specific test vector,which insulates the golden key information from the illegal users of chip.The proposed secure scan design with PUF key can also protect the crypto chips against all known scan-based side-channel attacks while incurring negligible overhead.This work implements a delay-based PUF based on parallel scan chain.It shows good uniqueness,randomness and reliability.This work also proposed a new secure scan design which incorporates the proposed PUF to implement different keys for the same lock in a design for mass production.The adoption of PUF enables the proposed scan design to be more secure against various typical scan-based side-channel attacks.As a security primitive,PUF is more promising in various fields of hardware security.More future work will hence focus on the application of PUF in other security designs.
Keywords/Search Tags:PUF, parallel scan design, secure scan design, scan-based side-channel attack
PDF Full Text Request
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