| As very large scale integrated circuits are designed into the deep sub-micron stage,chip performance continues to increase,posing challenges in many aspects such as timing,line length,and density.With the decrease of the process size,the interconnection delay is gradually increasing,and the interconnection delay becomes the key factor to determine the circuit performance.At present,three-dimensional integrated circuit design has become an important way to solve these problems.However,the three-dimensional chip design is not mature,it is difficult to quickly achieve timing closure.Therefore,the study of timing optimization of three-dimensional chip design has very great challenges and prospects.In order to solve the problem of layout timing optimization in VLSI physical design,this paper uses the Manhattan Path Greedy Method,Local Fine Grain Placement Method,Path Balance Method,Folding 3D Conversion Method and Hybrid Progressive Timing as the main goal.Dimensional layout method,in the layout process,fully consider the interconnection,modules,layers,silicon vias and the timing of the link between each other,designed and implemented two-dimensional and three-dimensional timing-driven layout device.And through the optimization of ISPD to provide high-performance ASIC benchmarks,showing the quality of the layout scheme to verify the layout of the program and the effectiveness of the algorithm.The results show that the standard performance of the two-dimensional time series is improved by 3%-6% compared to the original benchmarks,and the average performance of the three-dimensional time series optimization layout standard is increased by 7-12% on average.The implementation of timing-driven layout optimization will provide the corresponding technical support for the performance optimization of 2D and 3D chips independently developed by our country. |
