Research And Hardware Implementation Of NB-IoT Cell Search Algorithm

With the development of big data and 5G technology,more and more devices need to be connected to the network.Narrow Band Internet of Things(NB-IoT)is an important branch of low-power wide-area Internet of Things because of its low power consumption,low cost,wide coverage,and massive connections.As one of the key processes of the NB-IoT downlink receiver,cell search has a significant impact on the stability of the terminal equipment.Based on the narrow-band IoT protocol,this thesis studies the algorithm and hardware design of cell search,and designs a cell search algorithm that saves storage resources and a cell ID detection circuit.Compared with the Long Time Evolution(LTE),the NB-IoT narrowband secondary synchronization signal(NSSS)has more candidate sequences,which requires a large amount of storage space and makes the cell search algorithm more complicated.Aiming at this problem,this thesis designs a cell search algorithm that saves storage resources.By reasonably splitting the NSSS generation function and using the calculation module to get the value of some items,the use of memory is greatly reduced.In the calculation module,the phase offset is changed with the frame number.The special angle phase shift is used instead of the complex multiplication method,which reduces the complexity of the algorithm and avoids frequent data reading.It effectively improves the cell search efficiency.The simulation results show that the algorithm can achieve more than 80%detection accuracy with a 100ms detection window when the signal-to-noise ratio is-12.6dB.In order to reduce the complexity of NB-IoT cell ID detection system,this thesis designs a cell search system consisting of data control module and calculation module.The control module is used to realize the traversal of the cell ID and the serial number and read the cross-correlation data.This architecture makes the cross-correlation process subject to timing control,and it is easier to implement the coherent accumulation algorithm.Time division multiplexing of the divider during calculation of division and modulo saves DSP resources.AX7020 is used for FPGA verification.From the perspective of resource usage,the system uses 17.5MB of BRAM,and the Flip-Flop resource usage rate is only 0.4%,indicating that the design achieves the purpose of saving storage resources.