Research And Design On 10bit High Speed Low Power SAR ADC In 55nm

In the current digital information era,as the interface of digital system and physical world,analog-to-digital converter is an essentially important module,whose performance is the bottleneck of the digital information system.Research on high-speed and low-power ADC to provide WIFI and other devices with more stable and durable power supply,making a good opportunity to boost the rapid development of IOT.With the development of advanced technology and asynchronous clock technology,successive-approximation-register analog-to-digital converter has been able to get rid of low speed label,gradually qualified for high resolution application in middle-to-high speed,retaining the traditional advantages,such as low-power,small-area,easy-integration and simple-structure.Compared with the other ADC architecture like Flash,this one has more obvious advantages,becoming a hot pot in the field of high-speed ADC in recent years.The paper makes a comparison among common ADC,and finally choose the successive-approximation-register ADC as the design architecture.Based on the application like WIFI 802.11,the paper proposed a 10 bit high-speed low-power ADC in SMIC 55 nm Standard CMOS technology,achieving an ENOB of 9.74 bit at 200MS/s with a 24.805 MHz sine-wave input signal,the SFDR is 81.2d B,dissipating 0.75 m W from 1.2V power supply,resulting a Fo M of 4.39 f J/conversion-step,reaching the desired target.The INL and DNL are +0.44/-0.40 LSB and +0.27/-0.39 LSB,respectively.The main works of this paper includes:Firstly,make an overview of the common ADC architectures,and determine a design architecture for the 10 bit high-speed low-power performance.Secondly,based on the chosen high-speed low-power SAR ADC architecture,introduce and analyze the related technologies,and propose a systematic design scheme,design and optimize some important circuit modules,such as bootstrapped sample-and-hold circuit,charge redistribution DAC,high-speed dynamic comparator,window-opening SAR logic,digital-error-correction circuit and clock pulse generator.The whole design achieves the desired performance.