The Verification Of SM4 Algorithm Module Based On UVM

As the verification work of the chip almost occupies more than half of the entire SOC R&D(research and development)cycle,it is the most important part of chip manufacturing and testing.Then how to effectively complete the verification of the chip has become a problem to be solved for the development of integrated circuits(ICs).Based on the UVM verification methodology,using System Verilog language,a verification platform for the SM4 algorithm module with flexible and reliable advantages is designed in this paper.By studying the internal architecture of the BYCD00 series chip and the internal structure of the SM4 algorithm module in the chip,the communication of the SM4 algorithm module in the chip is divided into two parts.A part of the interface communicates with the CPU via the AHB bus.The other part of the interface communicates with other modules via the interface signal in the SM4 algorithm module.Based on this,two independent and complete verification components relying on AHB bus driver and other module drivers were established,and two sets of Transaction for the two components were set up to package the data information to achieve efficient data transfer between the components;Two sets of virtual interface were established to realise the information interaction between the verification platform and the Design Under Test(DUT).And the phase mechanism is used to implement the organic linkage of the components in the verification platform,facilitating the control of the start and end of the entire verification platform.The verification platform includes incentive generation,design monitor,reference model,and analysis of the design results.The incentive generation module uses the sequence mechanism to generate a constrained random excitation,which simplifies the interface information of the verification platform,reduces the error rate of code,and increases the reliability of the verification platform.The reference model is built using System Verilog language and the use of transaction-level communication ensure the consistent communication mode of the verification platform.Parameterized transaction-level information is used to communicate between components in a parametric verification platform,which makes the verification platform have the advantages of strong reusability and facilitates the migration between different projects.The parallel simulation method is adopted by the verification platform,which increases the verification efficiency and effectively shortens the verification cycle.The script file is used by the verification platform to control the simulation speed,which makes the simulation speed controllable and increases the flexibility of the verification platform.Based on the performance and application of BYCD00 series chips,the verification requirements of the SM4 algorithm module are analyzed and the function test points are extracted in this paper.On this basis,multiple sets of verification test cases are designed and coverage information is extracted by the VCS simulator.In the results,coverage of function coverage reached 100%,and code coverage reached more than 95%.It totally meets the verification requirements and satisfies the new requirements of the current chip technology development for verification technology.