Design And Verification Of Serial Physical Layer Of RapidIO Interface In High Performance Microprocessor

The rapid development of various technologies,such as computers and multimedia,has driven the increasing of processor architecture and buffer speed,which has led to a rapid increase in the performance of microprocessors.Especially the kernel,and the development of the processor bus frequency can only lag far behind the development of the kernel.As a result,the traditional shared bus has been unable to meet the I/O requirements for high-performance processors,and it has not been able to efficiently process signals and quickly transfer data.In addition,the requirements for bandwidth,reliability,flexibility,and cost between board interconnections and chips are also increasing.In this severe situation,solving this problem urgently requires a new type of high-speed serial bus to improve system performance.The emergence of RapidIO bus provides a new way to solve this bottleneck problem.In the field of embedded systems,the RapidIO interconnection bus has high speed,high reliability,and low latency,which has caused researchers to pay attention to it and pay extensive attention to it.The main research content of this paper is a RapidIO bus interface on the Power PC architecture processor,and focuses on the following aspects,and then realizes the serial physical layer design and verification of the RapidIO interface on this high-performance processor.First of all,this article describes the research background of the topic in detail,and focuses on the development of the RapidIO bus at home and abroad,compares RapidIO bus and other traditional buses,and thus draws the necessity of this research topic and discusses the advantages of RapidIO.And its application.Then,the RapidIO bus protocol was studied in detail and the serial physical layer was designed.The three-layer structure of the protocol specification was introduced.The transmission principle of the bus transaction was analyzed.According to the design index,the serial physical layer was mainly divided into the transmission channel and Receiving the channel in two parts,completes the module division of the physical coding sublayer.The transmission channels mainly include: a control symbol generation module,a channel allocation module,and an 8B/10 B encoding module.The receiving channels mainly include: an 8B/10 B decoding module,a channel merging module,and a control symbol analyzing module.Finally,verify the serial physical layer of the RapidIO bus.This topic is mainly based on Cadence's VIP research,by learning SV,UVM verification language,build a UVM verification platform based on VIP components,mainly from the RapidIO bus as a host or slave mode,the interface I / O transactions and The message doorbell transaction was fully verified.Finally,the results were analyzed and verified,which indicated that the RapidIO bus designed in this project satisfies the requirements of the protocol.