Design And Verification Of MAC For Physical Layer Based On PCIe Protocol Stack

The development of computer architecture raises higher demands in the bandwidth of computer bus. PCI EXPRESS( PCIe),the Third Generation Input/Output standard presented by INTEL,is widely used in a variety of computing and communications platforms. PCIe bus adopts point to point transfer technique, which is different fro m PCI bus, that brings higher data transmission efficiency and more expansibility.The construction of PCI EXPRESS is similar to TCP/IP stack. To transmit data between TX and RX,the data stream should get through Transaction Layer,Data Link Layer and Physical Layer of both sides. As the lowest level of the stack, Physical Layer plays an irreplaceable role in the PCI EXPRESS structure. In the Physical Layer, it will realize serial/parallel conversion and insert clock signal into the serial data stream. All these above improve data transmission efficiency and avoid using clock bus while connecting devices that increases the expansibility of devices. The differential signal line can reduce EMI effectively which improves the operating frequency of the PCIe bus.The whole Physical Layer is composed of two parts:Logical Physical Layer and Electrical Physical Layer. The Media Access Control of PCIe(MAC)is the core of Logical Physical Layer and it is also the keypoint to operate the PCIe bus for it connects the Data Link Layer and Physical Layer. MAC is mainly composed of three funct ions: data transmission,data reception and link training. These correspond with TX,TX and LTSSM. The TX logic achieves Byte Stripping, encoding and serial/parallel conversion of data packages from Data Link Layer. The RX is the inverse process of the TX, it will transform the received serial data stream into parallel data stream. LTSSM is the key and difficult points of the whole design. LTSSM will train the link to initialize the Physical Layer, port configuration information and link state.This thesis is based on PCIe stack bus. By redesigning the stack to meet the data transmission requirement of multiple server chips. In the design there is an additional Network Layer act as router for the data transmission. This thesis uses flow diagrams,state diagrams and data port diagrams to further demonstrate the design transition and methodology of each module.This thesis uses Verilog to realize RTL code, it also realizes simulat ion, synthesis and place&route by using XIlinx ISE tool. After that, it builds platform for verification of entire design by System Verilog to verify the entire design. The validation results illustrate this design meets requirements of MAC.The design of MAC in this thesis achieves multi-channel transmission and improves the data transmission efficiency. It successfully connect 40-core CPU in practice, and this chip can run operating systems steadily.